Ferroelectric Thin-film Transistors Research Articles

High-Performance Ferroelectric Thin Film Transistors with Large Memory Window Using Epitaxial Yttrium-Doped Hafnium Zirconium Gate Oxide.

Preventing ferroelectric materials from losing their ferroelectricity over a low thickness of several nanometers is crucial in developing multifunctional nanoelectronics. Epitaxially grown 5 at. % yttrium-doped Hf0.5Zr0.5O2 (YHZO) thin films exhibit an atomically smooth surface, an ability to maintain ferroelectricity even at a thickness of 10 nm, and excellent insulating properties, making them suitable for use as gate oxides in ferroelectric thin film transistors (FeTFTs). Through the epitaxial growth of a YHZO/La0.67Sr0.33MnO3 (LSMO)/SrTiO3 (STO) heterostructure, YHZO effectively retains its ferroelectricity and orthorhombic single phase, leading to enhancing electron mobility (∼19.74 cm2 V-1 s-1) and memory window (3.7 V) in the amorphous InGaZnO4 (a-IGZO)/YHZO/LSMO/STO FeTFTs. These FeTFTs demonstrate a consistent memory function with remarkable endurance (∼106 cycles) and retention (∼104 s). Furthermore, they sustain a constant memory window even under ±6 V bias stress for 104 s and exhibit excellent stability even under ±6 V/1 ms pulse cycling for 107 cycles. For comparison, a transistor with the same structure was fabricated using epitaxial nonferroelectric LaAlO3 (LAO) and epitaxial undoped Hf0.5Zr0.5O2 (HZO) as alternatives to YHZO. This study presents a novel approach to exploit the potential of YHZO in FeTFTs, contributing to the development of next-generation logic-in-memory.

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Analog Synaptic Devices Based on IGZO Thin‐Film Transistors with a Metal–Ferroelectric–Metal–Insulator–Semiconductor Structure for High‐Performance Neuromorphic Systems

A ferroelectric thin‐film transistor (FeTFT)‐based synaptic device with an indium–gallium–zinc oxide (IGZO) channel and a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure is reported. The fabricated FeTFT exhibits a highly linear conductance response (|α| = 0.21) with a large dynamic range (Gmax/Gmin ≈ 53.2), although identical program pulses are applied to the device. In addition, because the inner metal layer of the FeTFTs has an MFMIS structure, the electric field is uniformly applied to the entire IGZO channel, which reduces the cycle‐to‐cycle variation (σ = 0.47%) in the conductance responses. In the system simulation with the measured synaptic characteristics, the high classification accuracy of ≈97.0% is achieved in the MNIST image set, verifying the feasibility of FeTFT‐based neuromorphic systems.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

Solution processed Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric for a non-volatile ferroelectric thin film transistor

Lithium niobate (LiNbO3) gate dielectric based SnO2 ferroelectric thin film transistor (FETFT) is fabricated by a simple solution processed technique. However, LiNbO3 alone is not a suitable candidate for a gate insulator of a TFT because of its low band gap. Therefore, Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric has been used that reduces the gate leakage current by an order of magnitude compared to the LiNbO3 only device. Moreover, ionic polarization of Li-Al2O3 thin films that originated from mobile Li+ of Li-Al2O3, compensate for the ferroelectric charge polarization of LiNbO3 film. By reducing gate leakage current and compensating ferroelectric charge polarization, it becomes possible to achieve ferroelectric memory retention up to 7.2× 103 s of time with a difference of ON/OFF state by 3 times whereas the reference LiNbO3 device almost merges to each other very quickly. Besides, these ferroelectric TFTs (FETFT) can operate within 2 V operating voltage due to the strong ionic polarization of the gate dielectric. The carrier mobility of 1.9 cm2. V−1.s−1, current ON/OFF ratio of 1.6⨭104 and subthreshold swing (SS) of 167 mV.decade−1 has been achieved under 2 V operation of this FETFT, whereas memory retention time has been studied at 0 V gate and 1 V drain bias.

Ferroelectric polarization-switching acceleration of sputtered Hf0.5Zr0.5O2 with defect-induced polarization of interlayer

Herein, ferroelectric properties of Hf0.5Zr0.5O2 (HZO) are analyzed by inserting various interlayers (ILs) underneath HZO in capacitors and ferroelectric thin-film-transistors (FeTFTs) with all-sputter-deposited metal/HZO/IL/Si (MFIS) stacks. Although all the HZO films have similar phase ratios regardless of the IL, only the MFIS stack with a TiOx IL exhibit polarization switching. To investigate the polarization due to the introduction of TiOx, the polarization of TiOx is checked. It is confirmed that the TiOx can be polarized by the movement of oxygen vacancies (OVs) depending on the electric-field direction, which accelerates the polarization switching of HZO. Therefore, the insertion of the TiOx IL results in a wide (3.4-V) memory window in the FeTFTs, since the IL suppress the leakage current by increasing the IL thickness and simultaneously accelerates the polarization switching of the HZO.

Low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors with metal–ferroelectric–metal–insulator–semiconductor structure

We investigate the low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors (FeTFTs) with a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. MFMIS FeTFTs are fabricated with different metal-to-FE area ratios (AM/AF's). It is revealed that the noise generation mechanism differs depending on the operation region [low and high drain current (ID) regions] and AM/AF. Excess noise in the low ID region is observed in the MFMIS FeTFTs with AM/AF's of 4 and 6 due to carrier mobility fluctuations. In the high ID region, the carrier number fluctuation generates the 1/f noise of the devices regardless of the AM/AF.

Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

Design Strategy to Improve Memory Window in Ferroelectric Transistors With Oxide Semiconductor Channel

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx layer between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.

Ferroelectric Content-Addressable Memory Cells with IGZO Channel: Impact of Retention Degradation on the Multibit Operation.

Indium gallium zinc oxide (IGZO)-based ferroelectric thin-film transistors (FeTFTs) are being vigorously investigated for being deployed in computing-in-memory (CIM) applications. Content-addressable memories (CAMs) are the quintessential example of CIM, which conduct a parallel search over a queue or stack to obtain the matched entries for a given input data. CAM cells offer the ability for massively parallel searches in a single clock cycle throughout an entire CAM array for the input query, thereby enabling pattern matching and searching functionality. Therefore, CAM cells are used extensively for pattern matching or search operations in data-centric computing. This paper investigates the impact of retention degradation on IGZO-based FeTFT on the multibit operation in content CAM cell applications. We propose a scalable multibit 1FeTFT-1T-based CAM cell composed of only one FeTFT and one transistor, thus significantly improving the density and energy efficiency compared with conventional complementary metal-oxide-semiconductor (CMOS)-based CAM. We successfully demonstrate the operations of our proposed CAM with storage and search by exploiting the multilevel states of the experimentally calibrated IGZO-based FeTFT devices. We also investigate the impact of retention degradation on the search operation. Our proposed IGZO-based 3-bit and 2-bit CAM cell shows 104 s and 106 s retention, respectively. The single-bit CAM cell shows lifelong (10 years) retention.

High performance, amorphous InGaZnO thin-film transistors with ferroelectric ZrO2 gate insulator by one step annealing

Ferroelectric thin film transistors (FE-TFTs) are of increasing interest for next generation memory applications. Post fabrication annealing plays a crucial role to induce ferroelectricity in the gate insulator used for FE-TFT. The one step post fabrication annealing can induce ferroelectric phase in the gate insulator and reduce the defects in the semiconductor channel layer. We report a new technique to induce the ferroelectricity in spray coated ZrO2 with sputtered amorphous InGaZnO (a-IGZO) capping layer by employing one-step annealing. We achieved a large memory window of 1.5 V, high ION/IOFF ratio of 1 × 107, and steep subthreshold swing (SS) of 0.12 V/decade by one step annealing at 550 °C. The low thermal expansion coefficient (≈ 4.31 × 10−6/K) of a-IGZO helps to induce polar orthorhombic phase by providing suitable mechanical stress to the underlying ZrO2 layer. This work provides a new approach to induce ferroelectricity in ZrO2 for high performance ferroelectric thin film transistors.

High-Performance Flexible Hf0.5Zr0.5O2 Ferroelectric Thin-Film Transistors on PI Substrate By Solution Process

Flexible electronics such as wearable electronics, electronic skins, implantable devices, and flexible displays are started influencing our lives in various aspects due to their lightweight, portability, and human-friendly interface. In these applications, nonvolatile memory (NVM) and synaptic devices are essential elements to implement high speed integrated circuits and neuromorphic computing at low power consumption. Perovskite-based ferroelectric (FE) materials such as Pb(Zr,Ti)O3 (PZT), BaTiO3 (BTO), and SrBi2Ta2O9 (SBT) have been studied widely because of their fast switching speed, large polarization, and high dielectric constant. However, it is very difficult to integrate these materials with conventional semiconductor technology owing to their poor compatibility with complementary metal-oxide-semiconductor (CMOS) technology. Therefore, hafnium (Hf) based FE-materials could be a suitable candidate for next-generation flexible electronics. Which exhibits immense prospects due to their excellent performance, CMOS compatibility, high scalability, and chemical simplicity with various dopants (Al, Zr, Gd, La, Sr, and Y). Among these, Zr-doped HfO2 (Hf0.5Zr0.5O2 (HZO)) has been attracted intensive attention because of its low annealing temperature and large remnant polarization.We study the inverted staggered structured flexible HZO FE-TFTs on polyimide (PI) substrate with zinc oxide (ZnO) as the active layer. A 50 nm molybdenum (Mo) layer was deposited by sputtering and patterned to form the gate electrode. Then, the HZO precursor solution was spin-coated at 2000 rpm for 30 s and cured at 250 °C on a hot plate for 5 min, followed by UV/O3 curing at 100 °C for 5 min in ambient air as a gate insulator (GI). Thereafter, the Al2O3 precursor solution was deposited as a capping layer on top of the HZO film using the same process steps but the rpm was 3500. The crystallization was performed by furnace annealing at 450 °C for 2 h in N2 environment. The thicknesses of HZO and Al2O3 films are 20 and 15 nm, respectively. Afterwards, the ZnO (25 nm) channel layer was deposited using spray pyrolysis at 350 °C substrate temperature. The ZnO and GI films were patterned sequentially to form the active island and via-hole, respectively. Finally, a 50 nm thick Mo film was sputtered and patterned to form the source/drain (S/D) electrodes.The origin of ferroelectricity in HZO GI was analyzed by grazing incidence X-ray diffraction (GI-XRD) measurement from film and drain current vs gate voltage (ID vs VGS), gate leakage current (IG), and drain current vs drain voltage (ID vs VDS) characteristics measurements from TFT structures using Agilent 4156C semiconductor parameter analyzer. Channel width and length were 50 and 10 μm, respectively.Fig. 1 (a) shows the schematic structure of an inverted staggered HZO FE-TFT on PI substrate. Fig. 1 (b) and (c) show the ID vs VGS characteristics with anticlockwise hysteresis of HZO and Al2O3 capped HZO TFTs on PI substrate. The Al2O3 capped HZO TFT exhibits clear ferroelectric property with a large memory window (MW) of ≈1.9 V. A thin Al2O3 capping layer on top of HZO enhances the microstructure and morphology of HZO even at a low annealing temperature of 450 °C and helps to induce the ferroelectricity in HZO GI. Fig. 1 (d) shows the photograph of the measurement setup of HZO FE-TFTs during electrical measurements under tensile stress at 2 mm. Fig. (e) and (f) exhibit the ID vs VGS and IG vs VGS characteristics with anticlockwise hysteresis of Al2O3 capped HZO FE-TFTs under different tensile stress, respectively. The ID vs VGS curves exhibit almost identical performance during forward and reverse bias at different bending radii without showing significant changes in the electrical characteristics. The MWs were evaluated under different bending radii and they show the almost same value of ≈1.9 V from flat state and down to 2 mm bent state. The corresponding IG vs VGS curves at different bending radii exhibit a clear butterfly shape with current peaks at about ±2 V. These findings indicate that the solution-processed flexible HZO FE-TFTs have high stability under mechanical stress and contain ferroelectricity even at 2 mm bending radius without deteriorating MW. Therefore, the low-cost solution-processed FE-HZO GI has significant potential to be employed in nonvolatile memory and synaptic devices for future flexible electronics. Figure 1

Vertical ferroelectric thin-film transistor array with a 10-nm gate length for high-density three-dimensional memory applications

Hafnia-based ferroelectric thin-film transistors (FeTFTs) are regarded as promising candidates for future nonvolatile memory devices owing to their low power consumption, high operational speed, and complementary metal–oxide–semiconductor compatibility. However, the scalability of hafnia-based materials and the feasibility of three-dimensional (3D) device fabrication should be confirmed for ultrahigh-density memory applications. In this work, we demonstrate that FeTFTs can be scaled down to a 10-nm dimension using the vertical structure with a hafnia-based ferroelectric gate insulating layer and an oxide semiconductor channel. We show that such vertical FeTFTs can be operated with an effective device size of 0.005 μm2, a fast operation speed of &amp;lt;100 ns, and a high endurance of 108 cycles. Additionally, the string-level NAND operation is demonstrated using the vertical FeTFT array. Finally, device simulation confirms the possibility of ultrahigh-density 3D ferroelectric NAND with 200 gate stacks. These results demonstrate the ultrahigh scalability of FeTFTs as a promising candidate for next-generation 3D nonvolatile memory.

CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks.

Convolutional neural networks (CNNs) have gained much attention because they can provide superior complex image recognition through convolution operations. Convolution processes require repeated multiplication and accumulation operations, which are difficult tasks for conventional computing systems. Compute-in-memory (CIM) that uses parallel data processing is an ideal device structure for convolution operations. CIM based on two-terminal synaptic devices with a crossbar structure has been developed, but unwanted leakage current paths and the high-power consumption remain as the challenges. Here, we demonstrate integrated ferroelectric thin-film transistor (FeTFT) synaptic arrays that can provide efficient parallel programming and data processing for CNNs by the selective and accurate control of polarization in the ferroelectric layer. In addition, three-terminal FeTFTs can act as both nonvolatile memory and access device, which tackle issues from two-terminal devices. An integrated FeTFT synaptic array with parallel programming capabilities can perform convolution operations to extract image features with a high-recognition accuracy.

Demonstration of synaptic characteristics of polycrystalline-silicon ferroelectric thin-film transistor for application of neuromorphic computing

In this work, the synaptic characteristics together with 5 bits (32 states) operation based on polycrystalline-silicon (poly-Si) ferroelectric thin-film transistor (FeTFT) with HfZrO x gate dielectric are demonstrated for the first time. A 1.2 V threshold voltage shift of memory window is obtained. The impacts of pulse time on the potentiation and depression states are studied by a modulation scheme with incremental pulse voltages. The potentiation and depression rates of the conductance (G d) states of FeTFTs are found to be asymmetric and become more severe when increasing the pulse time. In order to realize high recognition rate and accuracy of neuromorphic computing, low asymmetric nonlinearity of potentiation () and depression () of poly-Si FeTFTs can be achieved with the reduction of operation voltage. Low asymmetry = 0.71 and high G d ratio ∼40 of FeTFTs are obtained based on the small pulse time of 50 ns and low average potentiation/depression voltages of 2.63/–2.69 V. When the pulse time is increased from 50 to 150 ns, the average potentiation/depression voltages can be further reduced to ∼1.59/–1.69 V for low asymmetry = 0.25 due to the enhanced G d potentiation and depression rates, and the G d ratio is also reduced to 9.96 with the reduction of potentiation/depression voltages. The small pulse time and potentiation/depression voltages of FeTFTs are responsible for the polarization switching of the ferroelectric layer following the minor operation-loop. Compared to the depression state, it leads to more stable retention and endurance behavior of the potentiation state due to the different depolarization electric fields.

Flexible Ferroelectric Hafnia-Based Synaptic Transistor by Focused-Microwave Annealing.

Hafnia-based ferroelectric memory devices with excellent ferroelectricity, low power consumption, and fast operation speed have attracted considerable interest with the ever-growing desire for nonvolatile memory in flexible electronics. However, hafnia films are required to perform a high temperature (>500 °C) annealing process for crystallization into the ferroelectric orthorhombic phase. It can hinder the integration of hafnia ferroelectric films on flexible substrates including plastic and polymer, which are not endurable at high temperatures above 300 °C. Here, we propose the extremely low-temperature (∼250 °C) process for crystallization of Hf0.5Zr0.5O2 (HZO) thin films by applying a focused-microwave induced annealing method. HZO thin films on a flexible mica substrate exhibits robust remnant polarization (2Pr ∼ 50 μC/cm2), which is negligibly changed under bending tests. In addition, the electrical characteristics of a HZO capacitor on the mica substrate were evaluated, and ferroelectric thin film transistors (Fe-TFTs), using a HZO gate insulator, were fabricated on mica substrates for flexible synapse applications. Symmetric potentiation and depression characteristics are successfully demonstrated in the Fe-TFT memory devices, and the synaptic devices result in high recognition accuracy of 91.44%. The low-temperature annealing method used in this work are promising for forming hafnia-based Fe-TFT memory devices as a building block on a flexible platform.

The Impact of Contact Position on the Retention Performance in Thin‐Film Ferroelectric Transistors

Here, the simulation of the physical fields in an n‐type ferroelectric thin‐film transistor (FeTFT) with a bottom contact bottom‐gate configuration is demonstrated. In the off‐state, the intensity of the lateral electric field in the space charge region near the edge of the drain electrode is several times higher than the coercive field of the ferroelectric film, pinning the direction of polarization near the drain electrode along the channel. While the FeTFT switches from off‐state to on‐state, the vertical component of polarization near the drain edge is stronger than other parts near the channel. This enhances the depolarization field in this area so that the retention performance of the on‐state is worse than the off‐state. These results and methods benefit FeTFTs and are also valuable for floating‐gate memory and light‐emitting field‐effect transistors.

Enhancement of the Retention Characteristics in Solution-Processed Ferroelectric Memory Transistor with Dual-Gate Structure.

We demonstrated the enhancement of the retention characteristics in solution-processed ferroelectric memory transistors. For enhanced retention characteristics, solution-processed Indium Gallium Zinc Oxide (InGaZnO) semiconductor is used as an active layer in a dual-gate structure to achieve high memory on-current and low memory off-current respectively. In our dual-gate oxide ferroelectric thin-film transistor (DG Ox-FeTFT), while conventional TFT characteristic is observed during bottom-gate sweeping, large hysteresis is exhibited during top-gate sweeping with high memory on-current due to the high mobility of the InGaZnO. The voltage applied to the counter bottom-gate electrode causes variations in the turn-on voltage position, which controlled the memory on- and off-current in retention characteristics. Specifically, due to the full depletion of semiconductor by the high negative counter gate bias, the memory off-current in reading operation is dramatically reduced by 10⁴. The application of a high negative counter field to the dual-gate solution-processed ferroelectric memory gives a high memory on- and off-current ratio useful for the production of high performance multi-bit memory devices.

Oxide semiconductor-based ferroelectric thin-film transistors for advanced neuromorphic computing

Neuromorphic computing that mimics the biological brain has been demonstrated as a next-generation computing method due to its low power consumption and parallel data processing characteristics. To realize neuromorphic computing, diverse neural networks such as deep neural networks (DNNs) and spiking neural networks (SNNs) have been introduced. DNNs require artificial synapses that have analog conductance modulation characteristics, whereas SNNs require artificial synapses that have conductance modulation characteristics controlled by temporal relationships between signals, so the development of a multifunctional artificial synapse is required. In this work, we report a ferroelectric thin-film transistor (FeTFT) that uses zirconium-doped hafnia (HfZrOx) and indium zinc tin oxide (IZTO) for neuromorphic applications. With reliable conductance modulation characteristics, we suggest that the FeTFT with HfZrOx and IZTO can be used as an artificial synapse for both DNNs and SNNs. The linear and symmetric conductance modulation characteristics in FeTFTs result in high recognition accuracy (93.1%) of hand-written images, which is close to the accuracy (94.1%) of an ideal neural network. Also, we show that the FeTFTs can emulate diverse forms of spike-time-dependent plasticity, which is an important learning rule for SNNs. These results suggest that FeTFT is a promising candidate to realize neuromorphic computing hardware.