Ferroelectric Thin-film Transistors Research Articles

An efficient device model for ferroelectric thin-film transistors

Ferroelectric thin-film transistors (Fe-TFTs) have promising potential for flexible electronics, memory, and neuromorphic computing applications. Here, we report on a physics-based efficient device model for Fe-TFTs that effectively describes memory switching and device I–V characteristics. This model combines a stochastic multi-domain description of FE switching dynamics with a virtual source treatment of TFT device characteristics. It demonstrates that the memory window of Fe-TFTs depends on the amplitude and duration of the applied voltage pulses, thus suggesting quantitative means of programming and control. Additionally, we introduce a machine-learning-enabled method to automatically generate optimal voltage pulses for accurately programming multiple intermediate FE states, which is crucial for multi-bit memory and neuromorphic computing applications. To showcase the model’s applications, we simulate a 4×4 crossbar array circuit based on Fe-TFTs, highlighting its utility in performing multiply-accumulate computing operations. This small array can achieve a high speed of ∼1.28 tera operations per second (OPS) and a power efficiency of ∼0.43 W/PetaOPS. The model developed here is valuable for exploring the capabilities of Fe-TFTs in future flexible memory and computing technologies.

All-Ferroelectric Spiking Neural Networks via Morphotropic Phase Boundary Neurons.

Artificial neurons and synapses are crucial for efficiently implementing spiking neural networks (SNNs) in hardware. The distinct functional requirements of artificial neurons and synapses present significant challenges in the implementation of area- and energy-efficient SNNs. This study reports an all-ferroelectric SNN system through co-optimization of material properties and device configurations using wafer-scale atomic layer deposition. For the first time, a double-gate (DG) morphotropic phase boundary-based thin-film transistor (MPBTFT) is utilized for a leaky integrate-and-fire (LIF) neuron. The DG MPBTFT-based LIF neuron eliminates the need for capacitors and reset circuits, thereby enhancing area and energy efficiency. The DG configuration demonstrates various neuronal functions with high reliability. Co-optimizing materials and devices significantly enhance the performance and functional versatility of artificial neurons and synapses. Meticulous material engineering facilitates the seamless co-integration of DG MPBTFT-based neurons, ferroelectric thin-film transistor (TFT)-based synapses, and normal TFTs on a single wafer. All-ferroelectric SNN systems achieved a high classification accuracy of 94.9%, thereby highlighting the potential of DG MPBTFT-based LIF neurons for advanced neuromorphic computing.

Cost‐Effective and Fully Hardware‐Oriented Reservoir Computing Based on IGZO/HZO Ferroelectric Thin‐Film Transistor with Electrically and Optically Distinguishable States

AbstractHardware‐based reservoir computing (RC) systems provide benefits like energy efficiency and effective predictability. The implementation of different switching characteristics for the reservoir and readout layers requires the use of different types of devices or additional processing. However, an RC system with distinguishable switching characteristics obtained by changing stimulation on a single device is not identified yet, but it is appealing in terms of process simplicity and efficient processing costs. This study develops an RC system that uses ferroelectric thin‐film transistor (FeTFT) devices with an indium gallium zinc oxide channel and Hf0.5Zr0.5O2 ferroelectric layer for both networks. The nonvolatile FeTFT utilizes the remnant polarization properties of the ferroelectric layer through electrical stimulation, showing stable retention characteristics (104 s) and long‐term potentiation/depression. By using optical stimulation, the volatile FeTFT demonstrates short‐term characteristics, such as paired‐pulse facilitation, and a 4‐bit RC system. This proves that it is possible to meet the functional requirements of both the reservoir and readout networks by simply varying the type of stimulation applied to a single FeTFT. Finally, the fully FeTFT‐based RC system can recognize digit patterns from the Modified National Institute of Standards and Technology database with a high accuracy of 90.5%.

Emulating Low-Power Synaptic Plasticity in a Solution-Processed Oxide-Based Long Retention Memory Transistor with High Learning Accuracy.

The exploration of synaptic plasticity in metal-oxide-based ferroelectric thin-film transistors has been limited. As a perovskite ferroelectric material, LiNbO3 is widely studied; but its potential use as a neuromorphic device, like synaptic transistors, has not been realized. In this study, a solution-processed ferroelectric thin-film transistor (FeTFT) with an alternating layer of LiNbO3 and Li5AlO4 as a gate dielectric has been fabricated. This configuration reduces the depolarization field by leveraging the large ionic polarization of Li+ ions in the Li5AlO4 layer, while the wide bandgap helps mitigate the leakage current. FeTFT exhibits impressive transistor performance, including a saturation mobility of 0.478 cm2V-1 s-1, an on/off ratio of 3.08 × 103, and a low trap-state density of 1.3 × 1013 cm-2. Moreover, the device demonstrates good memory retention, retaining information for nearly 1 day. It successfully emulates synaptic plasticity, specifically short-term plasticity and long-term plasticity. Besides, a 94% training accuracy has been achieved through artificial neural network simulation. Notably, the FeTFT consumes minimal power, with energy consumption of approximately 3.09 nJ per synaptic event, which is remarkably low compared to other reported solution-processed FeTFT devices.

Improved Stability of BEOL-Compatible Highly Scaled Ultrathin InZnO Channel Ferroelectric Thin-Film Transistor With TiO₂ Interfacial Layer

Improved Stability of BEOL-Compatible Highly Scaled Ultrathin InZnO Channel Ferroelectric Thin-Film Transistor With TiO₂ Interfacial Layer

(Invited) Polarization Stability Improvement for Hf0.5Zr0.5O2-Based Ferroelectric Capacitor

The instability in polarization during the endurance test of Hf0.5Zr0.5O2 (HZO) ferroelectrics thin films including the wake-up and the fatigue are still major challenges for the development of HZO-based ferroelectric memories. In this work, we will review the proposed mechanisms of the instabilities in polarization including wake-up and fatigue of the HZO-based metal-ferroelectric-metal (MFM) capacitors. Then, the material processing techniques to address the issues of instabilities are provided. The in-situ deposition of electrode and ferroelectric layers by atomic layer deposition (ALD) attracted considerable attention as a promising solution. Owing to the improved interface quality, both the endurance characteristics and remanent polarization were enhanced. We have also developed a HfO2/ZrO2 superlattice structure to further enhance the ferroelectric endurance of the MFM capacitors. The superlattice MFM capacitors show wake-up free characteristics with excellent endurance. The device performances and endurance characteristics of ferroelectric thin film transistor will also be presented.

Thermal Effects on Monolithic 3D Ferroelectric Transistors for Deep Neural Networks Performance

Monolithic three‐dimensional (M3D) integration advances integrated circuits by enhancing density and energy efficiency. Ferroelectric thin‐film transistors (Fe‐TFTs) attract attention for neuromorphic computing and back‐end‐of‐the‐line (BEOL) compatibility. However, M3D faces challenges like increased runtime temperatures due to limited heat dissipation, impacting system reliability. This work demonstrates the effect of temperature impact on single‐gate (SG) Fe‐TFT reliability. SG Fe‐TFTs have limitations such as read‐disturbance and small memory windows, constraining their use. To mitigate these, dual‐gate (DG) Fe‐TFTs are modeled using technology computer‐aided design, comparing their performance. Compute‐in‐memory (CIM) architectures with SG and DG Fe‐TFTs are investigated for deep neural networks (DNN) accelerators, revealing heat's detrimental effect on reliability and inference accuracy. DG Fe‐TFTs exhibit about 4.6x higher throughput than SG Fe‐TFTs. Additionally, thermal effects within the simulated M3D architecture are analyzed, noting reduced DNN accuracy to 81.11% and 67.85% for SG and DG Fe‐TFTs, respectively. Furthermore, various cooling methods and their impact on CIM system temperature are demonstrated, offering insights for efficient thermal management strategies.

P‐20: Memory Window and Endurance Improvement of In‐Ga‐Zn‐O‐Based Ferroelectric Thin Film Transistors by Inserting In‐Ga‐Zn‐O Floating Gate

We prepared oxide semiconductor‐based ferroelectric thin‐film transistors (FeTFTs) with a floating gate for memory application. Depositing oxide semiconductor on HfZrOx (HZO) as a floating gate successfully induced a polar orthorhombic phase with a larger memory window and higher endurance than conventional floating gate material TiN.

High-Performance Ferroelectric Thin Film Transistors with Large Memory Window Using Epitaxial Yttrium-Doped Hafnium Zirconium Gate Oxide.

Preventing ferroelectric materials from losing their ferroelectricity over a low thickness of several nanometers is crucial in developing multifunctional nanoelectronics. Epitaxially grown 5 at. % yttrium-doped Hf0.5Zr0.5O2 (YHZO) thin films exhibit an atomically smooth surface, an ability to maintain ferroelectricity even at a thickness of 10 nm, and excellent insulating properties, making them suitable for use as gate oxides in ferroelectric thin film transistors (FeTFTs). Through the epitaxial growth of a YHZO/La0.67Sr0.33MnO3 (LSMO)/SrTiO3 (STO) heterostructure, YHZO effectively retains its ferroelectricity and orthorhombic single phase, leading to enhancing electron mobility (∼19.74 cm2 V-1 s-1) and memory window (3.7 V) in the amorphous InGaZnO4 (a-IGZO)/YHZO/LSMO/STO FeTFTs. These FeTFTs demonstrate a consistent memory function with remarkable endurance (∼106 cycles) and retention (∼104 s). Furthermore, they sustain a constant memory window even under ±6 V bias stress for 104 s and exhibit excellent stability even under ±6 V/1 ms pulse cycling for 107 cycles. For comparison, a transistor with the same structure was fabricated using epitaxial nonferroelectric LaAlO3 (LAO) and epitaxial undoped Hf0.5Zr0.5O2 (HZO) as alternatives to YHZO. This study presents a novel approach to exploit the potential of YHZO in FeTFTs, contributing to the development of next-generation logic-in-memory.

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

Exploration of structural influences on the ferroelectric switching characteristics of ferroelectric thin-film transistors.

In this paper, quantitative analysis was performed focusing on the structural effect on the ferroelectric switching of ferroelectric thin-film transistors (FeTFTs). FeTFTs and ferroelectric capacitor (FeCap) test element groups (TEGs) were designed and fabricated, and positive-up-negative-down (PUND) measurements were performed to analyze the switching characteristics of ferroelectric films in various structures constituting an FeTFT. It was verified that TiN/HZO/a-IGZO/Mo (MFSM, FeTFT source/drain contact) mostly contributed to the memory operation of an FeTFT, while TiN/HZO/a-IGZO (MFS, FeTFT channel) exhibits one-time memory operation with irreversible polarization switching. In addition, the switching characteristics of MFSM and MFS were different from those of MFM, especially after a few cycles, related to the oxygen vacancy migration between a-IGZO channels and HZO films. The extracted 2Pr values for MFS, MFSM and TiN/HZO/Mo (MFM, FeTFT source/drain parasitic capacitor) were 38, 28 and 20 [μC cm-2], respectively. Based on the operation differences according to the device structure, it was found that irreversible switching in the MFS region (channel) causes a rapid decrease in the memory window after the first switching in an FeTFT and degradation of a-IGZO and HZO films in the MFSM region (contact) including oxygen vacancy exchange and related defect generation causes subthreshold slope increases and negative threshold voltage shifts as cycling stress was applied.

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Fully Electrically Modulated Hetero-Synapses With Lateral Multigate Ferroelectric Thin Film Transistor

Ferroelectric Hafnia-Based M3D FeTFTs Annealed at Extremely Low Temperatures and TCAM Cells for Computing-in-Memory Applications.

In order to overcome the bottleneck between the central processor unit and memory as well as the issue of energy consumption, computing-in-memory (CIM) is becoming more popular as an alternative to the traditional von Neumann structure. However, as artificial intelligence advances, the networks require CIM devices to store billions of parameters in order to handle huge data traffic demands. Monolithic three-dimensional (M3D) stacked ferroelectric thin-film transistors (FeTFTs) are one of the promising techniques for realizing high-density CIM devices that can store billions of parameters. In particular, oxide channel-based FeTFTs are well suited for these applications due to low-temperature processes, nonvolatility, and 3D integration capability. Nevertheless, the M3D-integrated CIM devices including hafnia ferroelectric films need the high-temperature annealing process to crystallize the ferroelectric layer, making M3D integration difficult. When the FeTFTs are fabricated with an M3D structure, the high-temperature process causes thermal issues in the underlying devices. Here, we present the focused microwave annealed (FMA) oxide FeTFTs with M3D integration at a low temperature of 250 °C. We confirmed that the FeTFTs with metal-ferroelectric-metal-insulator-semiconductor structure exhibited a large memory window of 3.2 V, good endurance over 106 cycles, and a long retention time of 105 s. To understand the different electrical characteristics of FeTFTs in the top and bottom layers, we experimentally analyzed the density of the state of the oxide channel and ferroelectric properties of the ferroelectric gate insulator by using multifrequency capacitance-voltage measurement and nucleation-limited-switching model analysis, respectively. With our approach, we demonstrate for the first time a vertical stacked FeTFTs-based ternary-content-addressable memory (TCAM) cell for CIM application. We believe that the proposed M3D-stacked TCAM cells composed of FeTFTs can be used in high-density memory, energy-efficient memory, and CIM technology.

Analog Synaptic Devices Based on IGZO Thin‐Film Transistors with a Metal–Ferroelectric–Metal–Insulator–Semiconductor Structure for High‐Performance Neuromorphic Systems

A ferroelectric thin‐film transistor (FeTFT)‐based synaptic device with an indium–gallium–zinc oxide (IGZO) channel and a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure is reported. The fabricated FeTFT exhibits a highly linear conductance response (|α| = 0.21) with a large dynamic range (Gmax/Gmin ≈ 53.2), although identical program pulses are applied to the device. In addition, because the inner metal layer of the FeTFTs has an MFMIS structure, the electric field is uniformly applied to the entire IGZO channel, which reduces the cycle‐to‐cycle variation (σ = 0.47%) in the conductance responses. In the system simulation with the measured synaptic characteristics, the high classification accuracy of ≈97.0% is achieved in the MNIST image set, verifying the feasibility of FeTFT‐based neuromorphic systems.

Fabrication of non-volatile memory transistor by charge compensation of interfacial ionic polarization of a ferroelectric gate dielectric

Lithium niobate (LiNbO3) is a popular lead free perovskite ferroelectric materials, but its implementation as a gate dielectric for developing a ferroelectric thin film transistor (FeTFT) has not been investigated much due to its low band gap. Low band gap introduces high gate leakage current that results in very low retention time of the device. In this report a solution processed Li5AlO4/LiNbO3/Li5AlO4 stacked layer has been used as a gate dielectric of a metal oxide thin film transistor which reduces gate leakage current by four orders of magnitude with respect to the single layer LiNbO3 gate dielectric device. Besides, due to the ionic polarization of Li5AlO4 thin film that originated from the mobile Li+, charge compensation of the depolarization field has been nearly removed. By reducing these factors, it becomes possible to fabricate metal oxide based FeTFT that has retention time of 7 h which is ∼200 times higher with respect to the LiNbO3 only FeTFT. The ratio of On and Off state of FeTFT is ∼103 which retains ∼ 95% after 7 h of operation. The carrier mobility, ON/OFF ratio and subthreshold swing (SS) of this FeTFT are 2.9 cm2 V − 1 s − 1,7.2 × 104 and 328 mV.decade−1 respectively.

Solution processed Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric for a non-volatile ferroelectric thin film transistor

Lithium niobate (LiNbO3) gate dielectric based SnO2 ferroelectric thin film transistor (FETFT) is fabricated by a simple solution processed technique. However, LiNbO3 alone is not a suitable candidate for a gate insulator of a TFT because of its low band gap. Therefore, Li-Al2O3/LiNbO3/Li-Al2O3 stacked gate dielectric has been used that reduces the gate leakage current by an order of magnitude compared to the LiNbO3 only device. Moreover, ionic polarization of Li-Al2O3 thin films that originated from mobile Li+ of Li-Al2O3, compensate for the ferroelectric charge polarization of LiNbO3 film. By reducing gate leakage current and compensating ferroelectric charge polarization, it becomes possible to achieve ferroelectric memory retention up to 7.2× 103 s of time with a difference of ON/OFF state by 3 times whereas the reference LiNbO3 device almost merges to each other very quickly. Besides, these ferroelectric TFTs (FETFT) can operate within 2 V operating voltage due to the strong ionic polarization of the gate dielectric. The carrier mobility of 1.9 cm2. V−1.s−1, current ON/OFF ratio of 1.6⨭104 and subthreshold swing (SS) of 167 mV.decade−1 has been achieved under 2 V operation of this FETFT, whereas memory retention time has been studied at 0 V gate and 1 V drain bias.

Ferroelectric polarization-switching acceleration of sputtered Hf0.5Zr0.5O2 with defect-induced polarization of interlayer

Herein, ferroelectric properties of Hf0.5Zr0.5O2 (HZO) are analyzed by inserting various interlayers (ILs) underneath HZO in capacitors and ferroelectric thin-film-transistors (FeTFTs) with all-sputter-deposited metal/HZO/IL/Si (MFIS) stacks. Although all the HZO films have similar phase ratios regardless of the IL, only the MFIS stack with a TiOx IL exhibit polarization switching. To investigate the polarization due to the introduction of TiOx, the polarization of TiOx is checked. It is confirmed that the TiOx can be polarized by the movement of oxygen vacancies (OVs) depending on the electric-field direction, which accelerates the polarization switching of HZO. Therefore, the insertion of the TiOx IL results in a wide (3.4-V) memory window in the FeTFTs, since the IL suppress the leakage current by increasing the IL thickness and simultaneously accelerates the polarization switching of the HZO.

Low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors with metal–ferroelectric–metal–insulator–semiconductor structure

We investigate the low-frequency noise characteristics of indium–gallium–zinc oxide ferroelectric thin-film transistors (FeTFTs) with a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. MFMIS FeTFTs are fabricated with different metal-to-FE area ratios (AM/AF's). It is revealed that the noise generation mechanism differs depending on the operation region [low and high drain current (ID) regions] and AM/AF. Excess noise in the low ID region is observed in the MFMIS FeTFTs with AM/AF's of 4 and 6 due to carrier mobility fluctuations. In the high ID region, the carrier number fluctuation generates the 1/f noise of the devices regardless of the AM/AF.

Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

Design Strategy to Improve Memory Window in Ferroelectric Transistors With Oxide Semiconductor Channel

Oxide semiconductors are promising channel materials for hafnia-based ferroelectric transistor memories because they can constrain the formation of an unwanted interfacial layer that can deteriorate the stability of the device. A major obstacle is the limited memory window, originating from insufficient polarization switching because <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductors cannot provide sufficient hole carriers to realize ferroelectric polarization switching. To solve this issue, a novel design strategy is proposed to achieve increased polarization switching while maintaining the stability of oxide semiconductor-based ferroelectric thin-film transistors (FeTFTs). By inserting an additional <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx layer between the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type oxide semiconductor InZnOx and ferroelectric HfZrOx, increased polarization switching is achieved owing to the high electron and hole densities in the InZnOx and CuOx layers, respectively. Thus, a memory window of 4 V is achieved, which cannot be obtained using a single oxide-semiconductor channel. We also demonstrate that the proposed method is viable for three-dimensional ferroelectric NAND (3D FeNAND) devices. In 3D FeNAND, replacing the dielectric filler with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type CuOx maximizes polarization switching and enlarges the memory window. The results demonstrate a novel structure and fabrication method for high-performance FeTFTs for advanced 3D non-volatile memory applications.