FEOL Process Research Articles

Hardware Performance Monitoring Methodology at Near-Threshold Computing and Advanced Technology Nodes: From Design to Postsilicon

Near-threshold computing is essential for energy-efficient operation of VLSI systems, but wide performance variation and nonlinearity to process variations block the proliferation. To cope with this, in this article, we propose a holistic hardware performance monitoring methodology for accurate timing prediction in a near-threshold voltage regime. Precisely, 1) we formulate the problem of finding an efficient configuration of monitoring circuits into an instance of optimal experiment design problem and 2) propose a new timing prediction flow, consisting of statistical estimation of FEOL and BEOL process variations and a neural network-based timing inference model. For accurate control of timing margin and overcoming simulation-silicon discrepancies, 3) we introduce uncertainty learning in the prediction model construction and calibrate it through transfer learning. Furthermore, 4) we avoid time-consuming SPICE simulations in our methodology by employing efficient but accurate surrogate models. Through simulations using a 28-nm industry PDK and DK characterized at 0.6-V operation, it is shown that our methodology is highly effective, reducing the average prediction pessimism of maximum delay by 77.9% over conventional signoff results while respecting target prediction yield. Besides, for test chips fabricated using a 10-nm process, we demonstrated that our holistic approach from design to postsilicon phase in conjunction with adaptive voltage scaling reduces dynamic power consumption by 28.2%–28.8% on average, in comparison with typical supply voltage operation.

Post Cleaning for FEOL CMP with Silica and Ceria Slurries

For the manufacturing of Si-based semiconductors, CMP is utilized extensively to enable FEOL process integration such as STI, deep-trench, ILD, and poly-open. Silica slurries are usually adopted for bulk oxide polish while ceria slurries are more suited for the final “buff” polish where high selectivity to nitride is required. The ever stringent requirement for scratch reduction leads to the trend of using nano-sized abrasive particles in all types of CMP slurries. However, the stronger adhesion force between these nanoparticles and wafer surface necessitates the re-design and optimization of post-CMP processes to meet the low PR/FM defect requirement. The selection of proper chemicals is often the first step towards post-CMP cleaning. However, design of cleaning sequence, exploitation of the tool hardware, and optimization of operating parameters are equally critical to achieve maximum cleaning efficiency. As shown in Fig. 1, for an oxide or poly-Si CMP process with an acidic silica-based slurry, a preferred post cleaning process should operate in alkaline environment (e.g., pH 8~10) in order to build in repulsive zeta potential for easy of particle removal from wafer surface. In this case, the use of an acidic pCMP chemical would be unfavorable from zeta-potential point of view. Replacement of acidic chemical with just DIW (pH ~ 7) leads to significant reduction in PR/FM. In addition, optimization of the directionality, spin rpm, arm oscillation speed…etc, helps eliminate the wafer center-heavy signature and reduces the defect count further down. For FEOL CMP with ceria-based slurry running on a 3-platen polisher with serial meg tank/brush cleaning module, one can design the pCMP process based on the unique “reactive” nature of ceria abrasives, and also fully exploit the available hardwares and their process parameters. In this example, the POR process adopts only DIW in the meg tank. The go-to process, however, replaces DIW with a diluted acidic oxidizer so as to neutralize the reactive ceria abrasives, making it much easier to dislodge the particles from oxide wafer surface. The significant FM NADD reduction with the go-to pCMP process illustrates the efficiency of adding the meg clean step with diluted oxidizer. Further PR/FM reduction can be realized by optimizing the hardware and machine parameters such as those listed in Fig. 2, from on-platen buff clean all the way to the terminal step of Maragoni drying. Furthermore, for a new pCMP process to be considered production-ready, run order effects, repeatability, and CoO reduction need to be taken into account as well. In addition, post-clean surface analyses are carried out to ensure no potential reliability concern. Reference: W.-T. Tseng, J. Hagan, K. Mohan, R. Hull, J. MacDougall, R. Murphy, L. Tai, S. Molis, “Post Cleaning and Defect Reduction for Tungsten Chemical Mechanical Planarization” ICPT, 2015. Figure 1

Reduced Anisotropy in Tetramethylammonium Hydroxide Based Silicon Etchants

At sub-10 nm technology nodes, silicon etching is critical to FEOL processes such as FinFET thinning, gap filler removal, pre-III-V deposition etch, and nanowire release etching. The key to developing solutions for these applications is being able to control the anisotropy of the Si etch, or the etch selectivity between Si (111), Si (100), and Si (110). For this study, we focused on the impact of modifications to tetramethylammonium hydroxide (TMAH) on Si etch selectivity, with the ultimate goal of developing an isotropic Si etchant based on TMAH. Initial studies focused on etch selectivity testing of TMAH based chemistries on Si (SOI) wafers of varying orientations. Etch rates were based on measuring thickness changes by cross-sectional SEM. Differences in surface roughness were also characterized by atomic force microscopy. Finally, solutions were evaluated for anisotropy by performing an etch of patterned pSi wafers. As expected, aqueous TMAH solutions showed a high level of anisotropy (111/100/110 = 1:5:5) and significant level of surface roughening. In contrast, some of the modified TMAH solutions tested had decreased surface roughening and an decreased level of anisotropy (111/100/110 = 1:2:2). Pattern etching on implanted pSi wafers is used to highlight the differences in anisotropy between TMAH and the different modifications.

Reduced Anisotropy in Tetramethylammonium Hydroxide Based Silicon Etchants

At sub-10 nm technology nodes, silicon etching is critical to FEOL processes. One of the keys to developing solutions for these applications is being able to control the anisotropy of the Si etch, or the etch selectivity between <111>, <100>, and <110>. We have focused on the impact of modifications to tetramethylammonium hydroxide (TMAH) on Si etch selectivity, with the ultimate goal of developing an isotropic Si etchant based on TMAH. As expected, aqueous TMAH solutions showed a high level of anisotropy (<111>:<100>:<110> = 1:5.5:5.1) and significant level of surface roughening. In contrast, some of the modified TMAH etch solutions tested had decreased surface roughening and a decreased level of anisotropy (<111>:<100>:<110> = 1:1.6:1.1). Pattern etching on implanted pSi wafers is used to highlight the differences in anisotropy between TMAH and the modifications.

Evaluation of InGaAs and InP Compatibility with Alkaline Photoresist Stripping Formulations

III-V semiconductors, such as InGaAs, are leading contenders to replace Si as high-mobility channel materials for sub-10 nm finFETs.(1,2) Implementation of these high-mobility materials into FEOL processes faces many challenges because of the chemical sensitivity and complex nature of these materials relative to the conventional Si channel. In particular, damage from wet cleaning solutions is a major concern that needs to be understood and controlled when designing new cleaning formulations for use in the manufacture of III-V based devices. Herein, we will describe our work at understanding InGaAs and InP compatibility with formulated alkaline photoresist strippers with a focus on the impact of solvent and alkaline component selection. Initial studies focused on etch rates of InGaAs and InP in a series of proprietary cleaning chemistries. InGaAs films (500 Å) on InP – as well as bulk InP – wafers were used for this study. Etch rates were determined by energy-dispersive X-ray spectroscopy (EDX) as well as by gallium and arsenic leaching via ICP-MS. While acidic chemistries in general showed excellent compatibility, alkaline- and amine-based chemistries displayed varying levels of compatibility with InGaAs. Because of the range of compatibilities observed in alkaline chemistries, we explored the impact of solvent and alkali selection as well as water content on selectivity. Specifically, we evaluated a series of non-proprietary solutions using a selection of solvent types, alkaline components, and water content (semi-aqueous vs. non-aqueous). The impacts of these components will be discussed and compared to results previously presented for GaAs etched in these same chemistries.(3) For the strippers that are reported to be highly compatible with InGaAs and InP, a more thorough analysis of surface changes will be reported including changes in roughness (AFM) and composition (XPS). The results and key learnings from this study will be discussed in relation to how InGaAs and InP may be cleaned with limited surface damage. 1) International Technology Roadmap for Semiconductors, see www.itrs.net2) J. A. del Alomo, Nature, 479, 317 (2011). 3) G. Westwood, SEMATECH Surface Preparation and Cleaning Conference, Austin, TX, 2012.

Physical Cleaning Enhancement Using Advanced Spray with Uniform Droplet Control

In semiconductor device manufacturing, single wafer processors are widely used in not only BEOL process but also in FEOL process for 2X devices to improve the cleaning efficiency and get the higher productivity. Because the scaled down devices require the minimum substrate loss in the cleaning steps, the physical force by a dual fluid spray is still the main position to improve the cleaning efficiency at the moment comparing with chemical effects as the dissolution of contaminants and/or the lift off of particles. Sato, et al., reported that the relationship between particle removal and droplet characteristics linked to the droplet energy densityEdas following equation [. The kinetic energyEkof droplet is calculated from droplet diameterdand velocityv, as shown in Equation 1.

Cleaning and Surface Preparation for SiGe and Ge Channel Device

Since silicon will ultimately face physical limitations, germanium and III-V materials, such as Ga, GaAs, InGaAs, are being extensively investigated for their high electron and hole mobility advantages. Prior to implementing germanium or III-V materials, it is believed that SiGe with high Ge concentration will be applied for channel materials in pMOS devices with high-k and metal gates in order to simultaneously adjust the work function and to increase the hole mobility. However, introduction of new channel materials leads to new challenges and substantial changes in the FEOL process flow.

Cleaning Challenges and Solutions for Advanced Technology Nodes

Trends in further scaled CMOS technologies are reviewed with respect to the implications for cleaning and wet processing. Particularly the FEOL processes are being considered such as selective cap removal, pre-epi cleaning and post I/I photo resist removal. For technologies beyond the 15nm Ge and III-V are being considered. Several aspects of wet processing of these materials and advanced integration schemes are covered.

Stripping of Ion Implanted Photoresist by CO&lt;sub&gt;2&lt;/sub&gt; Cryogenic Pre-Treatment Followed by Wet Cleaning

In FEOL processing, doping of active areas like source, drain, and extensions (NMOS and PMOS) is done by ion implantation. Un-doped regions are covered with photoresist to protect them from implantation. Ion implantation modifies the surface of the photoresist to generate a dehydrogenated amorphous carbon layer, the crust [1]. When the implant conditions are more aggressive (higher implant energy and implant dose), the hard crust becomes more and more challenging to be removed [2]. Conventionally, a plasma ashing process followed by a wet cleaning, typically SPM (Sulfuric acid/Hydrogen peroxide mixture) chemistry, can remove the implanted photoresist, but usually leads to damage and strong oxidation of the underlying semiconductor material and hence result in material or dopant loss. As the technology node migrates beyond 45nm, the photoresist removal process should also be compatible with novel materials such as high-k dielectric and metal-gate used in advanced gate stack integration. For these reasons, it is desirable to eliminate the plasma ash and SPM clean chemistry. Wet only PR removal process is studied using new chemistries like solvents that are compatible with the other FEOL process steps, however, the photoresist removal using solvents only still showed lower removal efficiency than conventional processes. It has been demonstrated that the CO2 cryogenic pre-treatment can improve the ion implanted photoresist stripping efficiency of the wet cleaning processes [3], and can also enhance the photoresist removal efficiency by the solvents.

F34 Applications of X-ray reflectivity to develop and monitor feol and beol processes for sub-65nm technology nodes

F34 Applications of X-ray reflectivity to develop and monitor feol and beol processes for sub-65nm technology nodes