Fault Tolerance Features Research Articles

An improved finite set model predictive control of SRM drive based on a voltage vectors strategy for low torque ripple

The robust rotor structure and fault-tolerance characteristics of the Switched Reluctance Motors (SRMs) are the best choice for next-generation Electric Vehicle (EV) applications. This machine has few restraints like high torque and flux ripples. However, the existing Model Predictive Control (MPC) using multiple control objectives and maximum sectors in the switching table results in high torque ripples due to the improper sector partition, Voltage Vectors (VVs) and weight factor (K1) selection. This paper proposes a Finite Set-Model Predictive Control (FS-MPC) for an analytical model of a non-linearity SRM machine to analyze the torque ripple performance. The proposed VVs are derived using sector partition based on the rotor position. The control is designed as a single cost function with the weighting factor contributing to smooth torque by selecting optimal control signals. Simulation studies and experiments with a four-phase 8/6 SRM drive verifies the enhanced FS-MPC for real-time implementation. The dynamic speed and ripple values of SRM Drives are measured using a mixed signal oscilloscope and the sensor probes. The laboratory outcomes calculate the analytical equations to validate the findings. The calculated value of torque ripple is 9 % through this FS-MPC. The study reveals that the proposed method is well suited for torque ripple reduction than flux ripples.

Stability analysis and anti-windup design of saturated switching systems based on multiple Lyapunov functions

Abstract In this paper, employing advanced multiple Lyapunov functions (MLF) technology, we conduct a thorough investigation into the fault-tolerant characteristics of actuator saturation-based systems, particularly those prone to failures. Based on this comprehensive analysis, we carefully design an anti-windup (AW) controller, incorporating an efficient AW compensator and precisely calibrated gains for the dynamic state feedback controller, tailored to meet the specific needs of practical control systems. To further demonstrate the effectiveness of our approach, we also provide a detailed numerical example.

Ethical Knowledge Sharing Leveraging Blockchain: An Overview

The knowledge that is acquired through a learning process has ethical concerns when shared, as there can be restrictions on the parties who can use the piece of knowledge, redistribution approaches protecting the creator's rights, privacy, and confidentiality concerns, accuracy and trustworthiness, openness and transparency, and informed consent. Blockchain structure encompasses a series of coupled blocks that are intrinsically linked with the conservation of authenticity, ensuring irrefutability, and the semi-anonymity of transactions. As pioneers in reviewing BC-based ethical Knowledge Sharing (KS), we categorize the model into 4 classes and critically evaluate the literature relative to knowledge-associated features, ethical knowledge-sharing aspects, BC-associated features, and network features. We heaped a commencing sample of 69 document references by selecting the literature for eligibility conditions pursued from intellectual resource search platforms, leveraging a profound and overly extended-period technique. We investigate and emphasize that, owing to innate security properties, blockchain can facilitate ethical KS in numerous ways, such as leveraging a dedicated consensus approach for ethical KS (Class 1), leveraging blockchain itself for knowledge storage and sharing due to its mutation-proof, non-tamperable, fault tolerance features (Class 2), ensuring the confidentiality of knowledge by leveraging additional encryption techniques on blockchain (Class 3), and leveraging smart contracts for attribute-based searching, knowledge fusion, access control, reward-driven KS, etc. (Class 4). Critical evaluation unveils that from BC-based ethical KS frameworks, 50% utilize smart contracts with blockchain for knowledge-based activities, 90% leverage progressive BC architecture, 6.7% leverage proof-of-knowledge consensus, 93.4% share propositional knowledge, and 70% share explicit knowledge. Moreover, accuracy, openness and transparency, privacy, trustworthiness, truthfulness, and confidentiality have been the dominant factors in ethical KS principles of interest. Finally, we examine the openings and hurdles of the model of blockchain-based ethical KS, then propose actions to diminish them, and afterward present future directions, implications, and limitations for the concept.

A Novel Single-Phase Five-Level Current-Source Inverter Topology

Recent technological advances have renewed the research interest in current-source inverters (CSIs). Nonetheless, CSI research still falls behind its voltage-source counterpart with regards to topologies, modulation, and control. Acknowledging the above, this paper presents a novel single-phase five-level CSI topology. The proposed circuit utilises eight switches and two inductors for the generation of five distinct output levels while maintaining low output voltage THD and dv/dt. Furthermore, by offsetting the inductor currents from a binary 1:2 to a trinary 1:3 ratio, the proposed inverter can generate seven current levels at its output. The inverter offers built-in short-circuit protection and can boost a low input DC voltage to a higher peak AC output voltage. These merits, alongside an electrolytic-capacitor-free design, simple current balancing mechanism, and fault-tolerant characteristics, make it a promising candidate for PV module-integrated inverter (MII) systems. The current topology utilises two inductors but is fully functional with single-inductor operation. The paper provides a functional analysis of the inverter topology alongside the inverter switching states and corresponding conduction paths. A detailed analysis of the inductor current dynamics as well as a current-balancing algorithm for dual- and single-inductor operations are given. The theoretical analysis of the proposed circuit and its functional operation are verified using simulations and experimental results carried out on a laboratory prototype.

Design and Fabrication of Switched Reluctance Motor for Energy Efficient Operation by Minimizing Torque Ripple

Around the world, motor is consuming more than 40% of the total-generated electrical energy. Accordingly, energy efficient electrical drives are the needs of the hour. The Switched Reluctance Motor (SRM) is more energy efficient than other kinds. Since SRM has a rugged structure, it has inherent fault tolerance characteristics and is cost-effective than synchronous and induction machines. Nevertheless, the application of such a motor is limited due to low torque density, torque ripples and power losses because of control circuit. In this research work, the author proposed a novel-designed SRM, which is achieved by optimizing stator and rotor pole arc. Alongside, a novel control circuit, which has single transistor, is proposed. The modification of stator and rotor pole arcs assists in the reduction of the torque ripple. The stator pole arc is modified from 32 degree to 36 degree, and the rotor pole arc is modified from 30 degree to 28 degree. Thus, the torque ripple is reduced from 3.25 to 2.92 Nm, and thus, the useful torque is increased from 4.94 to 5.2 Nm. Furthermore, a single transistor switching device is used instead of the conventional one with four switches. Hence, energy loss on the control circuit is significantly reduced. From the experimental analysis, it is found that, with-pole-arc modified SRM has higher efficiency than the one without it.

Optimization of layout for embedding half hypercube into conventional tree architectures

SummaryEmbedding a graph into another graph can be utilized for structural simulation, processor allocation, and algorithm porting in the field of parallel architecture. This has the potential to enhance the physical layout of network‐on‐chip (NoC) devices as well as to investigate their virtualization possibilities. Layout is one of the many indicators of graph embedding. An optimal layout in NoC design can result in a decreased wiring area and cost, as well as the reduction in communication delay between parallel processing components. In this work, the guest graph is the half hypercube, which possess efficient routing, fault tolerance, and Hamiltonian features. The edge isoperimetric problems is solved for the half hypercube using a novel technique called the isochronal ordering. The host graphs considered in our work are complete binary trees, ‐rooted complete binary trees, and other few predominantly investigated tree based architectures.

METHODOLOGY OF DATASET COLLECTING FOR AN AUTHENTIFICATION TASK BASED ON A FACE THERMOGRAPHIC IMAGE

This paper discusses the issues of training machine learning models for people authentication by the face image in longwave infrared radiation. The analysis of public available and freely distributed datasets of other researchers in the field, which contain images of people’s faces in infrared range, are discussed. It was concluded, that it is necessary to form a dataset for training and testing machine learning models on one’s own. To obtain the highest results using trained methods in practical purposes a list of requirements for the collected dataset was developed. In conclusion, an experiment was conducted, where the machine learning method (logistic regression) was trained on each dataset and tested on a sample of 15 images combining each dataset (75 images totally). During the experiment it was discovered, that the algorithm trained on the collected dataset successfully copes with both: the task of authenticating user by his thermal imaging on theoretical datasets and in the practical one. The results obtained can be used in access control and management systems to increase the fault tolerance characteristics for person authentication. The use of this dataset allows the model training aimed at theoretical and practical use in the tasks of processing thermograms, for the person authentication by the pattern of veins and vascular networks on the face in cases of changes in appearance and environmental conditions.

Approach to Evaluate Scheduling Strategies in Container Orchestration Systems

This article offers an in-depth examination of scheduling strategies in container orchestration systems, emphasizing the importance of selecting the most suitable strategy for a system's specific needs. The article explores the evolution of container systems and challenges around cloud reliability and fault tolerance. A structured experimental methodology was introduced to compare different strategies systematically, utilizing various testing methods like packing until first rejection, packing until the cluster is full, and introducing different malfunctions such as liveness and network partitioning. Comparative results between the “binpack” and “spread” strategies highlighted that while the former excels in higher scheduling requests acceptance rate, the latter is superior in offering higher availability. The findings show the need for aligning the scheduling strategy with system objectives, be it resource optimization, fault tolerance or other desired characteristics

GA evolved CGP configuration data for digital circuit design on embryonic architecture

Embryonic architecture that carries self-evolving design with fault tolerant feature is proposed for deep space missions. Fault tolerance is achieved in the embryonic architecture due to its homogeneous structure. The cloning of configuration data or genome data to all the embryonic cells makes each cell capable of selecting required cell function using selective gene. The primary digital circuits of avionics are implemented on the fabric, where the configuration data in Cartesian Genetic Programming (CGP) format is evolved through customized GA. The CGP format is preferred over LUT format for the circuit configuration data due to its fixed data size in case of modular design. Further the CGP format enables fault detection at embryonic cell level as well as logic gate level. The various combinational and sequential circuits like adder, comparator, multiplier, register and counter are designed and implemented on embryonic fabric using Verilog. The circuit performance is evaluated using simulation. The proposed PHsClone genetic algorithm (GA) design with parallel-pipeline approach is to achieve faster convergence. Four concurrent PHsClone GA executions (four parallel threads) achieve convergence for the 10 times faster for a 1-bit adder, and 3 times faster for a 2-bit comparator.

Benchmarking Criteria for A Cloud Data Warehouse

The Terasort benchmark and the YCSB benchmark are the two most used cloud computing benchmarks. Despite the fact that these benchmarks are quite helpful, data warehouse systems and associated OLAP technologies were not the focus of their creation. We initially introduce cloud computing and data warehouse systems in this essay. Then, we contend that the TPC-H benchmark, which is the most well- known benchmark for decision support systems, conflicts with the justifications for cloud computing (scalability, elasticity, pay-per-use, fault-tolerance characteristics), and customer relationship management (end- user satisfaction, Quality of Service features). Finally, we propose updated specifications for a benchmark for cloud data warehouse systems. The suggested specifications ought to make it possible to fairly compare the products offered by various cloud system providers.

On the performance and scalability of consensus mechanisms in privacy-enabled decentralized renewable energy marketplace

Renewable energy sources were introduced as an alternative to fossil fuel sources to make electricity generation cleaner. However, today’s renewable energy markets face a number of limitations, such as inflexible pricing models and inaccurate consumption information. These limitations can be addressed with a decentralized marketplace architecture. Such architecture requires a mechanism to guarantee that all marketplace operations are executed according to predefined rules and regulations. One of the ways to establish such a mechanism is blockchain technology. This work defines a decentralized blockchain-based peer-to-peer (P2P) energy marketplace which addresses actors’ privacy and the performance of consensus mechanisms. The defined marketplace utilizes private permissioned Ethereum-based blockchain client Hyperledger Besu (HB) and its smart contracts to automate the P2P trade settlement process. Also, to make the marketplace compliant with energy trade regulations, it includes the regulator actor, which manages the issue and consumption of guarantees of origin and certifies the renewable energy sources used to generate traded electricity. Finally, the proposed marketplace incorporates privacy-preserving features, allowing it to generate private transactions and store them within a designated group of actors. Performance evaluation results of HB-based marketplace with three main consensus mechanisms for private networks, i.e., Clique, IBFT 2.0, and QBFT, demonstrate a lower throughput than another popular private permissioned blockchain platform Hyperledger Fabric (HF). However, the lower throughput is a side effect of the Byzantine Fault Tolerant characteristics of HB’s consensus mechanisms, i.e., IBFT 2.0 and QBFT, which provide increased security compared to HF’s Crash Fault Tolerant consensus RAFT.

An Enhanced Distributed Control Architecture of Multiple Three-Phase PMSG for Improving Redundancy

Multiple three-phase permanent magnet synchronous generator (MTP-PMSG) has excellent fault-tolerant features in theory. However, the commonly used control architectures, such as the centralized control architecture with only one central controller and the distributed control architecture where the interconnected communication cables between controllers may fail, limit the fault tolerance of MTP-PMSG. Therefore, this paper proposes an enhanced distributed control (EDC) architecture without interconnected communication cables of MTP-PMSG for improving redundancy. The sensorless control and harmonic current suppression algorithm are considered and implemented in the EDC architecture. First, this paper analyzes the magnetic field coupling between the winding sets of MTP-PMSG, and the variation law of equivalent inductance of the winding sets under the condition of arbitrary current sharing is obtained. Then, an enhanced distributed sensorless control (EDSC) method in EDC architecture is proposed based on the equivalent inductance. Furthermore, this paper proposes a model-free predictive harmonic current (MFPHC) suppression method to solve the MTP-PMSG's inherent harmonic problem in the EDC architecture. The effectiveness of the proposed methods is verified by the comparative simulations and experiments in a dual three-phase PMSG (DTP-PMSG) with arbitrary current sharing of winding sets.

An NPC‐type fault‐tolerant MLI with symmetrical and asymmetrical voltage modes

SummaryCurrent studies have been challenging in reducing the number of devices and ensuring fault tolerance features of the multilevel inverters (MLIs). This article proposes a new fault‐tolerant neutral point clamped (NPC)‐type MLI using two three‐level NPC legs, which can work in symmetric and asymmetric modes to generate nine and 17‐level output voltage, respectively. The proposed converter has less device count and low total blocking voltage (TBV); further, the converter has different redundant switching states for tolerating different categories of faults. This article also implements a modified pulse width modulation (PWM) control strategy to ensure the zero‐dc offset at the output when asymmetrical voltage levels appear with the occurrence of switch faults. A detailed operation of the proposed converter under symmetric and asymmetric modes is presented for healthy and different categories of faults. The converter's feasibility is verified by its current and voltage characteristics obtained from the MATLAB‐SIMULINK software and the experimental prototype. Further, the efficiency of the converter is verified with the PLECS software. Finally, a comparison with recently proposed topologies is performed to emphasize converter performance.

TS-WHT: A Two-Step Walsh–Hadamard Transform Approach for Blind Error Correcting Code Classification

Blind classification of error-correcting codes is essential for intelligent wireless communication, cognitive radio, and non-cooperative communication. The object of this paper is to investigate the differences in the Walsh spectrum between linear block code, convolutional code, and Turbo code. Based on these differences, a two-step Walsh Hadamard transform (TS-WHT) strategy is proposed for error-correcting code blind classification. Further, according to the detection theory, the peak detection threshold is detailed and optimized with the cyclic feature of CRC codes. The results indicate that when employing the optimized threshold, probabilities of correct classification are superior for linear block codes and convolutional codes. Moreover, with the help of the fault-tolerant feature of the WHT technique, the classification accuracy of the proposed method is substantially better than existing approaches under low signal-to-noise ratio(SNR) conditions.

A new hybrid algorithm integrating genetic algorithm with Tabu search to solve imbalanced k‐coverage problem in directional sensor networks

AbstractThe target coverage problem is considered as one of the major issues in directional sensor networks (DSNs), which is caused by the nature of these networks, including their limited angle of view. Due to the fault tolerance characteristic of some coverage applications, the target coverage is required to be performed using multiple sensors. This challenge is discussed in the literature under the title of k‐coverage problem. Under certain conditions, the number of sensors may suffer some changes due to various factors such as power depletion of the sensors, sensors' malfunctioning, and harshness of the environment. This can result in unavailability of adequate sensors for providing k‐coverage for all targets. The network suffering from such problem is referred to as under‐provisioned network. This paper was aimed at studying such networks by adopting the network conditions to the real environments. To solve this problem, the present paper proposes a hybrid model integrating the genetic algorithm (GA) and Tabu search (TS). The proposed algorithm generally aimed to identify a subset of sensors with appropriate working directions in order to provide a balanced coverage for all the targets available in the network. In order to evaluate the performance of the algorithm several experiments were conducted and the results have been compared with greedy and learning automat‐abased algorithms. . The results of the experiments show the superiority of the algorithm.

Scalable and fault-tolerant selection method of verification and accounting nodes for permissionless blockchain

The transaction processing mode of the permissionless blockchain with the PoW protocol is to generate transaction block through network-wide competition and perform transaction verification by all the nodes jointly, resulting in wasted computing power resources and low throughput as bottlenecks for its application in industrial fields with high-frequency transactions. In order to enhance the transaction processing performance of the blockchain system and meet the actual security requirements, we propose a scalable and fault-tolerant selection method of verification and accounting nodes. Firstly, combined with the advantages of PoW, we apply the computationally difficult problem in the selection method of the verification set, which can fully utilize computing resources and ensure the efficiency of transaction verification. Afterwards, a fault-tolerant selection method of accounting node is designed by constructing the verifiable random number using threshold signature, which can ensure the robust operation of the system in the presence of malicious nodes. The newly developed method has the following advantages: it has fault-tolerant characteristics; the method can be applied to systems with Byzantine or non-Byzantine errors, and is appropriate for practical application scenarios. It has compatibility, the method can be seamlessly integrated into Byzantine fault tolerance, crash tolerance, threshold voting and other consensus protocols to improve the performance of the protocol. It has versatility, the method can be applied to both single blockchains and sharding blockchains to demonstrate its versatility and flexibility. Finally, the results of the security analysis and experiment show the method is of superiority and effectiveness.

DNA Arithmetic with Error Correction.

DNA design approaches are expected to play an important role in the future design of non-silicon-based computers. However, one of the main challenges for its mass fabrication is the considerable error rate. This paper presents a DNA computing system based on the Redundant Residue Number system (RRNS) that has elegant fault-tolerance features. The proposed method is the first to introduce the sticker model into DNA Arithmetic based on RRNS. The ability of error detection and correction are advantages of the proposed computing system. Moreover, the proposed arithmetic method can operate on large DNA-represented numbers, since RNS split them into smaller numbers. The implementation of arithmetic operations on these small numbers decreases the probability of failure in DNA operations.

The use of reversible logic gates in the design of residue number systems

Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.

Multiport DC-DC Converter with Differential Power Processing for Fast EV Charging Stations

With the growing interest in owning electric vehicles due to increased environmental awareness and uncertain energy security together with the development of Li-ion batteries, quietness, and trouble-free operation, it is urgent to develop charging stations that are fast enough to supply the vehicles with energy conveniently, as in case of conventional petrol stations. The main reason that hinders the spread of fast charging stations is the installation cost, comprising the infrastructure and converter costs. In this article, a multiport DC-DC converter with differential power processing stages is proposed for Electric Vehicle (EV) fast charging stations, which results in a considerable reduction in the cost of using converters while achieving high efficiency. The proposed topology consists of two paths for the power flow (outer and inner loops) for EV battery charging with main and auxiliary DC-DC converters in the outer loop; all the ports are connected in series with the main supply, where the bulk power is being transferred. The main DC-DC converter injects a series voltage to control the power in the outer loop. The auxiliary DC-DC converters are rated at a fractional power that controls the partial power supplied to each port through the inner loops. Thanks to the fractional power processed by the auxiliary converter with the remaining power fed to the battery through the main converter, the proposed architecture enables simultaneous charging of multiple electric vehicles with better efficiency, lower cost, and the capability of providing a fault tolerance feature. A PWM control scheme for the converters to achieve bi-directional power flow in the partially rated DC-DC converters is discussed for the proposed system. Moreover, a practical down-scaled hardware prototype is designed to validate the functionality, control scheme, and effectiveness of the proposed topology in different case studies being investigated. The efficiency of the proposed converter is compared to the conventional configuration.

Fault-Tolerant and Self-Reliant Characteristic in Series Resonant Converter for Semiconductor Open/Short-Circuit Faults

With the increased popularity of series resonant converter (SRC) in grids and microgrids, a robust converter with fault-tolerant (FT) feature becomes supremely important. A single-switch primary-side failure results in half of the pre-fault voltage and lesser power at the output. While a secondary-side short-circuit (SC) fault results in negligible voltage and power, leading to discontinuous converter operation. For more than one switch fault on any side, the SRC behavior in the post-fault condition is different. This article analyses the self-reliant characteristic in SRC for single/two-switch open-circuit (OC) and SC fault. A post-fault correction is proposed, which maintains the continuity of operation and the rated output voltage at the load for different fault conditions. An FT capacitor is used along with the control parameter variation in the post-fault correction for a single-switch and different combinations of two-switch faults. The proposed method is also applicable for single-diode SC or OC fault. The analysis of the self-reliant feature and the post-fault correction is discussed and tested on a 1 kW, 250 V SRC prototype for different fault conditions.