Faults In Synchronous Sequential Circuits Research Articles

VLSI-based self-healing solution for delay faults in synchronous sequential circuits

The paper evolves a methodology in an effort to heal the occurrence of delay faults in synchronous sequential circuits. The delay fault appears to be critical in the operation of digital circuits owing to the large number of gates integrated on a chip and manifests themselves in the incorrect timing behaviour of some logic elements within the network. The scheme allows detection of a wider range of delay faults with improved resolution and envisages measures to restore the true values at the primary output through appropriate changes in the structure. It uses saboteurs for fault injection and handles delay faults both in combinational and memory blocks of synchronous sequential circuit. The approach turns out to be comparatively simple and helps to improve the long-term reliability of high-performance digital circuits besides enabling to decrease the cost and area overhead over the existing triple modular redundancy (TMR) and distributed minority and majority voting-based redundancy (DMMR) fault healing schemes. The fact that the Spartan architecture synthesises the VLSI codes foster to validate the MODELSIM-based simulated results and perpetuates a claim for its use in real world digital utilities.

VLSI-based self-healing solution for delay faults in synchronous sequential circuits

The paper evolves a methodology in an effort to heal the occurrence of delay faults in synchronous sequential circuits. The delay fault appears to be critical in the operation of digital circuits owing to the large number of gates integrated on a chip and manifests themselves in the incorrect timing behaviour of some logic elements within the network. The scheme allows detection of a wider range of delay faults with improved resolution and envisages measures to restore the true values at the primary output through appropriate changes in the structure. It uses saboteurs for fault injection and handles delay faults both in combinational and memory blocks of synchronous sequential circuit. The approach turns out to be comparatively simple and helps to improve the long-term reliability of high-performance digital circuits besides enabling to decrease the cost and area overhead over the existing triple modular redundancy (TMR) and distributed minority and majority voting-based redundancy (DMMR) fault healing schemes. The fact that the Spartan architecture synthesises the VLSI codes foster to validate the MODELSIM-based simulated results and perpetuates a claim for its use in real world digital utilities.

Very Large Scale Integrated Solution for Stuck at Faults in Synchronous Sequential Circuits

Very Large Scale Integrated Solution for Stuck at Faults in Synchronous Sequential Circuits

TOV: Sequential Test Generation by Ordering of Test Vectors

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan

Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic

Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.

On redundant path delay faults in synchronous sequential circuits

A path delay fault in a sequential circuit will affect circuit timing only if it can be activated during normal operation of the circuit. Since vector pairs that can be applied to the next-state logic of a nonscan sequential circuit are restricted by the available state transitions, some faults may be impossible to activate. Such faults are redundant and need not be tested. In this paper, we present a method of identifying redundant path delay faults in the next-state logic implemented in a two-level sum of products form and extend it to multilevel realizations. Experimental results on MCNC'91 benchmarks show that large fractions of faults in most of the MCNC'91 benchmarks are redundant.

SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

Testing of synchronous sequential circuits for path delay faults requires two sequences: a test sequence, that specifies the input values, and a clocking scheme, that specifies at what time units a fast clock should be applied. In this work, a fault simulator for path delay faults in synchronous sequential circuits is described, that has the following novel features. (1) For a given test sequence, all clocking schemes that have a single fast clock are simulated in parallel. (2) During the simulation process, it is possible to determine a minimal set of clocking schemes to achieve the same fault coverage as in (1). (3) Alternatively, it is possible to simulate the test sequence under a given clocking scheme, containing multiple fast clocks at arbitrary time units. (4) A path representation scheme is used, that allows efficient access to path delay faults detected by previous tests. Experimental results are presented to demonstrate these features and their effectiveness. >

Path delay fault simulation of sequential circuits

To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transition conditions for two consecutive vectors. After the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flip-flop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The simulation is independent of the specific delays of the combinational elements, and either robust or nonrobust detection can be simulated as options to the user. For robust simulation, an update rule for state variables is proposed whereby a flip-flop is updated with its correct value, provided it is a destination of at least one robustly activated path. This rule gives a higher and more realistic coverage of robustly detected faults. Experimental results verify the effectiveness of the simulator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Classification of faults in synchronous sequential circuits

Undetectable and redundant faults in synchronous sequential circuits are analyzed. A distinction is drawn between undetectable faults and faults that are never manifested as output errors. The latter are classified as redundant. It is shown that there are faults for which a test sequence does not exist; however, under certain initial conditions (or initial states) of the circuit, faulty behavior may be observed. Such faults are called partially detectable faults. A partially detectable fault is undetectable, but is not redundant, as it affects circuit operation under some conditions. The author observes that the notion of redundancy cannot be separated from the mode of operation of the circuit. Two modes of operation are considered, representative of common modes, called the synchronization mode and the free mode. Accordingly, the identification of redundant faults calls for different test generation strategies. Two test strategies to generate tests for detectable faults and partial tests for partially detectable faults are defined, called the restricted test strategy and the unrestricted test strategy. >

Modeling and Testing for Timing Faults in Synchronous Sequential Circuits

Even with proper design, integrated circuits and systems can have timing problems because of physical faults or variation of parameters. The authors introduce a fault model that takes into account timing related failures in both the combinational logic and the storage elements. Using their fault model and the system's requirements for proper operation, the authors propose ways to handle flipflop-to-flipflop delay, path selection, initialization, error propagation, race-around, and anomalous behavior. They discuss the advantages of scan designs like LSSD and the effectiveness of random delay testing.