Faults In Sequential Circuits Research Articles

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits

VLSI-based self-healing solution for delay faults in synchronous sequential circuits

The paper evolves a methodology in an effort to heal the occurrence of delay faults in synchronous sequential circuits. The delay fault appears to be critical in the operation of digital circuits owing to the large number of gates integrated on a chip and manifests themselves in the incorrect timing behaviour of some logic elements within the network. The scheme allows detection of a wider range of delay faults with improved resolution and envisages measures to restore the true values at the primary output through appropriate changes in the structure. It uses saboteurs for fault injection and handles delay faults both in combinational and memory blocks of synchronous sequential circuit. The approach turns out to be comparatively simple and helps to improve the long-term reliability of high-performance digital circuits besides enabling to decrease the cost and area overhead over the existing triple modular redundancy (TMR) and distributed minority and majority voting-based redundancy (DMMR) fault healing schemes. The fact that the Spartan architecture synthesises the VLSI codes foster to validate the MODELSIM-based simulated results and perpetuates a claim for its use in real world digital utilities.

VLSI-based self-healing solution for delay faults in synchronous sequential circuits

The paper evolves a methodology in an effort to heal the occurrence of delay faults in synchronous sequential circuits. The delay fault appears to be critical in the operation of digital circuits owing to the large number of gates integrated on a chip and manifests themselves in the incorrect timing behaviour of some logic elements within the network. The scheme allows detection of a wider range of delay faults with improved resolution and envisages measures to restore the true values at the primary output through appropriate changes in the structure. It uses saboteurs for fault injection and handles delay faults both in combinational and memory blocks of synchronous sequential circuit. The approach turns out to be comparatively simple and helps to improve the long-term reliability of high-performance digital circuits besides enabling to decrease the cost and area overhead over the existing triple modular redundancy (TMR) and distributed minority and majority voting-based redundancy (DMMR) fault healing schemes. The fact that the Spartan architecture synthesises the VLSI codes foster to validate the MODELSIM-based simulated results and perpetuates a claim for its use in real world digital utilities.

Very Large Scale Integrated Solution for Stuck at Faults in Synchronous Sequential Circuits

Very Large Scale Integrated Solution for Stuck at Faults in Synchronous Sequential Circuits

First Steps in Creating Online Testable Reversible Sequential Circuits

Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented using quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops and the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving upon the replacement technique in both quantum cost and ancilla inputs. We present here a further improved version of the direct feedback method. Design examples show that the proposed method produces better results than our earlier method in terms of both quantum cost and ancilla inputs. We also propose the first technique for online testing of single line faults in sequential reversible circuits.

정적 교정 제어기를 이용한 비동기 순차 회로의 내고장성 구현

비동기 순차 회로를 위한 교정 제어기는 회로를 재설계하지 않고도 회로 내에 존재하는 여러 고장을 탐지하고 극복하는 능력을 보인다. 이번 논문에서는 교정 제어기의 크기를 줄이기 위한 방법으로서 정적 교정 제어기(static corrective controller)를 제안한다. 동적 제어기에 비해 정적 제어기는 제어기 상태가 필요 없으므로 조합 회로(combinational circuit)만으로 구현 가능하다. 본 논문에서는 상태 천이 고장에 대한 정적 내고장성 교정 제어기가 존재할 조건과 설계 과정을 규명한다. 또한 제안된 제어 기법을 FPGA로 구현된 SEU 오류 카운터에 적용하여 그 효용성을 실험적으로 검증한다. Corrective controllers enable fault diagnosis and tolerance for various faults in asynchronous sequential circuits without resort to redesign. In this paper, we propose a static corrective controller in order to decrease the size of the controller. Compared with dynamic controllers, static controllers can be made using only combinational circuits, as they need no inner states. We address the existence condition and design procedures for static corrective controllers that overcome state transition faults. To show the validity and advantage, the proposed controller is applied to an SEU error counter implemented on FPGA.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

Simulation-based ATPG for low power testing of crosstalk delay faults in asynchronous circuits

A new multi–objective genetic algorithm has been proposed for testing crosstalk delay faults in asynchronous sequential circuits that reduces average power dissipation during test application. The proposed Elitist Non–dominated Sorting Genetic Algorithm (ENGA)–based Automatic Test Pattern Generation (ATPG) for crosstalk induced delay faults generates test pattern set that has high fault coverage and low switching activity. Redundancy is introduced in ENGA–based ATPG by modifying the fault dropping phase and hence a very good reduction in transition activity is achieved. Tests are generated for several asynchronous SIS benchmark circuits. Experimental results demonstrate that ENGA gives higher fault coverage, reduced transitions and compact test vectors for most of the asynchronous benchmark circuits when compared with those generated by Weighted Sum Genetic Algorithm (WSGA).

TOV: Sequential Test Generation by Ordering of Test Vectors

We describe a new approach to test generation for stuck-at faults in synchronous sequential circuits. Under this approach, the input vectors comprising the test sequence are fixed in advance. The process of generating the test sequence consists of ordering the precomputed input vectors such that the resulting test sequence has as high a fault coverage as possible. The advantage of this approach is that its computational complexity is limited by limiting the search space to a given set of input vectors and a given test sequence length. We describe a specific implementation of this approach. Experimental results demonstrate that restricting the search space to a fixed number of precomputed input vectors is sufficient for achieving the highest known fault coverage, or a fault coverage close to it, for benchmark circuits.

Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware

This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a circuit which implements a closest-match fault location algorithm specialized for the circuit under diagnosis (CUD). This method allows designers to perform dynamic fault location of stuck-at faults in large circuits, and eliminates the need for large storage required by a software-based fault dictionary. In fact, the approach is a pure hardware solution to fault diagnosis. We demonstrate the feasibility of the method in terms of hardware resources and diagnosis time by experimenting with ISCAS85 and ISCAS89 circuits. The emulation-based diagnosis method speeds up the diagnosis process by an order of magnitude compared to the software-based fault diagnosis. This speed-up is important, especially, when the on-line diagnosis of safety---critical systems is of concern.

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τk-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.

On generating tests that avoid the detection of redundant faults in synchronous sequential circuits with full scan

Design-for-testability (DFT) techniques used for synchronous sequential circuits allow redundant faults, which do not affect the functional operation of the circuit, to be detected after DFT insertion. Detecting such faults can cause a chip that operates correctly to be discarded as faulty. A solution proposed earlier was to mask output values where redundant faults are detected in the circuit with DFT, without masking other faults, which should continue to be detected. We investigate a complementary issue of generating test sets that require as little masking as possible. Our goal is to generate a test set that does not detect any redundant faults (or detects as few redundant faults as possible), such that no output values (or as few output values as possible) would have to be masked. We discuss the relationship of this problem to fault dominance. We then describe a specific procedure based on test selection for deriving test sets that detect as few redundant faults as possible while detecting all the other detectable faults.

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

We describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.

On masking of redundant faults in synchronous sequential circuits with design-for-testability logic

Design for testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. In this paper, we propose to deal with such faults by masking (or ignoring) their fault effects when they appear on the circuit outputs. This should be done without masking the detection of other faults of the original circuit, which need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of masked faults among the faults that should be detected.

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.

Diagnostic simulation of stuck-at faults in sequential circuits using compact lists

This article describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices, and for large circuits is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits with known deterministic tests. The diagnostic fault simulator has also been modified to diagnose defects, given the output responses of failing devices. Results on simulated bridging defects show that the diagnosis time is comparable to the time for fault simulation with fault dropping.

Test generation for sequential circuits using state transition diagram and test generation for combinatorial circuit part

AbstractThis study deals with single stuck‐at faults in sequential circuits; in particular, a test generation method featuring low generation complexity and short test sequences. With the proposed method, short test sequences are generated using shortest local connections between activation vector set found for combinatorial circuit part at gate level, and state transitions found from state transition diagram at functional level. Generated test sequences are input sequences composed of subsequences referred to as single test sequences. Single test sequences are composed of state control sequences that control activation vectors and their states, and UIO (Unique Input/Output) sequences that confirm states after applying activation vectors. Test sequences are generated so as to locally minimize total length of state control sequences and UIO sequences in connected single test sequences, which results in shorter test sequences as compared to previous generation methods. Evaluation experiments using MCNC benchmarks proved that test sequences generated by the proposed method were shorter by up to 28.8% as compared to previous methods while fault coverage was above 98% on the average. © 2001 Scripta Technica, Electron Comm Jpn Pt 2, 84(8): 20–28, 2001

Identification of primitive faults in combinational and sequential circuits

This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits. It uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits. The same technique is used to identify combinationally primitive faults in the next-state and output logic of sequential circuits. Such faults are primitive if and only if the fault effects on paths to state variable flip-flops can be propagated to a primary output (PO). Test sequences, including initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to POs, are generated for primitive faults, wherever possible. The proposed method has been implemented and used to derive tests for primitive faults in the ISCAS'89 and MCNC'91 benchmark circuits. It was able to find all primitive faults and also obtain robust tests for a large fraction of them when the circuits were treated as combinational. When the same circuits were treated as nonscan sequential circuits, all primitive faults could not be found because fault propagation had to be limited to a relatively small number of time frames.

Static test compaction for IDDQ testing of bridging faults in sequential circuits

This paper presents a static test compaction method for IDDQ testing of sequential circuits. Test compaction reduces test application time and tester memory and consequently reduces testing cost. Particularly for IDDQ testing, measurement of IDDQ is time-consuming, and thus test compaction is a very important issue. In the proposed method, test subsequences are removed and replaced with shorter subsequences by considering state transition of a circuit under test, so that original fault coverage is guaranteed. The effectiveness of the proposed method is demonstrated by experimental results for ISCAS'89 benchmark circuits. © 2000 Scripta Technica, Syst Comp Jpn, 31(11): 41–50, 2000

Path delay fault simulation of sequential circuits

A differential algorithm for concurrent simulation of path delay faults in sequential circuits is presented. The simulator analyzes all three conditions, namely, initialization, signal transition propagation through the path, and fault effect observation at a primary output for vector pairs and considers the hazard states occurring between vectors. The main contribution is in methods of propagating signals between time frames. An optimistic method assumes that all nondestination flip-flops are not affected by delays. The pessimistic method converts all nondestination flip-flops with nonsteady values to the unknown state before these values are propagated beyond the time frame in which a path is activated. A 13-valued algebra is shown to improve the efficiency of fault simulation.