Faults In Combinational Circuits Research Articles

Beware of Insufficient Redundancy

Fault injection attacks pose a serious threat to cryptographic implementations. Countermeasures beyond sensors and shields usually deploy some form of redundancy to detect or even correct errors. A few years ago, a novel design methodology called Impeccable Circuits has been introduced on how to correctly integrate Concurrent Error Detection (CED) schemes, based on Error-Detection Codes (EDCs), into cryptographic hardware circuits. The underlying adversary model limits attackers to inject at most t single-bit faults. By additionally considering the propagation of faults in combinational circuits, the countermeasure guarantees detection of any faulty computation caused by up to t single-bit faults.In this work, we present an experimental analysis of the Impeccable Circuits countermeasure and its underlying assumptions in modern semiconductor technology. More precisely, we have taken hardware implementations of the lightweight block cipher SKINNY equipped with various forms of the EDC-based CED schemes and realized them as cryptographic co-processors on a 40nm ASIC to experimentally evaluate their resistance to Laser Fault Injection (LFI) attacks. In short, our results show that it is fairly simple to overcome the protection offered by the integrated countermeasures when the length of the code n is smaller than twice its rank k (i.e., no full redundancy). This is not caused by any flaw in the underlying design methodology or concept, but merely demonstrates how easily the defined adversary model can be overcome. In our case, a standard black-box scan over the target using a common single-shot LFI setup is sufficient to occasionally inject more single-bit faults than those bounded by the underlying adversary model when n < 2k. The probability of such events proved to be large enough to perform successful key-recovery attacks via Differential Fault Analysis (DFA) in a matter of hours. Thus, we caution against limiting the redundancy in code-based FI countermeasures to less than the number of bits per word, especially in nanometer technologies, and point out that less-complex countermeasures like duplication showed a higher level of resistance in our experiments at a lower cost.

Recurrent neural networks models for analyzing single and multiple transient faults in combinational circuits

Transient faults analysis is an important step in circuits designing flow. By a fast and accurate scrutiny, it is possible to achieve a cost-effective and soft error tolerant system. In this paper, an efficient and accurate approach is presented to estimate the shapes of transient faults when they are propagating through the gate-level circuits. To provide a reliable prediction of how the shape of a transient fault occurring in a circuit will be, a new method based on recurrent neural networks (RNNs) is proposed. This method can make a confident estimation of the effects that the single/multiple transient faults leave while propagating through a combinational circuit. Results for a sample of 32-bit carry propagation adder shows 22x speed-up with a mean of 0.82 penalty in accuracy loss, compared to the HSPICE simulator.

Fault equivalence identification in combinational circuits using implication and evaluation techniques

Efficient identification of fault equivalence relations is essential for effective diagnostic test pattern generation. In this paper, we present efficient techniques for identifying functionally equivalent faults in combinational circuits. The techniques are based on implication of faulty values, and evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Both static and dynamic methods are developed to exploit relations among inputs of dominator cones and further speed up the identification of equivalent fault pairs. Experimental results for all ISCAS'85 circuits, full scan versions of ISCAS'89 circuits, and ITC'99 circuits show that most of the equivalent fault pairs are identified. Significant reductions are obtained in the runtime needed to prove equivalence and the runtime for diagnostic test pattern generation compared to previously proposed approaches.

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that [email protected] vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% reduction in test set size, test data volume and test application time compared to a state-of-the-art native transition test ATPG tool, without any reduction in fault coverage. Other benefits of our approach, viz. productivity improvement, constraint handling and design data compression are highlighted.

On diagnosing multiple stuck-at faults using multiple and single fault simulation in combinational circuits

Diagnosing multiple stuck-at faults in combinational circuits using singleand multiple-fault simulation is proposed. The proposed method adds (removes) faults from a set of suspected faults depending on the result of multiple-fault simulation at a primary output agreeing (disagreeing) with the observed value. However, the faults that are added or removed from the set of suspected faults are determined using single-fault simulation. Diagnosis is carried out by repeated addition and removal of faults. The effectiveness of the diagnosis method is evaluated by experiments conducted on benchmark circuits and it is found to be substantially superior compared to the previous known solutions. The method proposed in this paper can be used as a powerful tool at the preprocessing stage of diagnosis in an electron-beam tester environment.

ATPG tools for delay faults at the functional level

We present an ATPG tool for functional delay faults which applies to the single-input transition (SIT) and the multi-input transition (MIT) fault models, and is based on Reduced Ordered Binary Decision Diagrams (ROBDDs). We are able, for the first time, to identify all faults that do not have any SIT tests, and generate all SIT tests for nonredundant faults in combinational circuits. We also provide methodologies for efficient generation of MIT tests. Our experimental results on the ISCAS'85 benchmarks is by far superior to existing methods as well as a Satisfiability-based tool that we have developed for comparative purposes. The presented tool, coupled with advancements in path delay fault coverage, shows that both the SIT and MIT functional models are very useful in ATPG for robust path delay faults for synthesized circuits.

Sequential Circuits with Combinational Test Generation Complexity under Single-Fault Assumption

We show that the test generation problem for all single stuck-at faults in sequential circuits with internally balanced structures can be reduced into the test generation problem for single stuck-at faults in combinational circuits. In our previous work, we introduced internally balanced structures as a class of sequential circuits with the combinational test generation complexity. However, single stuck-at faults on some primary inputs, called separable primary inputs, corresponded to multiple stuck-at faults in a transformed combinational circuit. In this paper, we resolve this problem. We show how to generate a test sequence and identify undetectability for single stuck-at faults on separable primary inputs.

An exact solution to the minimum size test pattern problem

This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.

ATPG for combinational circuits on configurable hardware

In this paper, a new approach for generating test vectors that detects faults in combinational circuits is introduced. The approach is based on automatically designing a circuit which implements the D-algorithm, an automatic test pattern generation (ATPG) algorithm, specialized for the combinational circuit. Our approach exploits fine-grain parallelism by performing the following in three clock cycles: direct backward/forward implications, conflict checking, selecting next gate to propagate fault or to justify a line, decisions on gate inputs, and loading the state of the circuit after backup. In this paper, we show the feasibility of this approach in terms of hardware cost and speed and how it compares with software-based techniques.

Identification of primitive faults in combinational and sequential circuits

This paper presents a method of primitive fault identification and test generation for combinational and nonscan sequential circuits. It uses the concept of sensitizing cubes to obtain input vectors that statically sensitize primitive faults in combinational circuits. The same technique is used to identify combinationally primitive faults in the next-state and output logic of sequential circuits. Such faults are primitive if and only if the fault effects on paths to state variable flip-flops can be propagated to a primary output (PO). Test sequences, including initializing sequences from a reset state and sequences that propagate fault effects from flip-flops to POs, are generated for primitive faults, wherever possible. The proposed method has been implemented and used to derive tests for primitive faults in the ISCAS'89 and MCNC'91 benchmark circuits. It was able to find all primitive faults and also obtain robust tests for a large fraction of them when the circuits were treated as combinational. When the same circuits were treated as nonscan sequential circuits, all primitive faults could not be found because fault propagation had to be limited to a relatively small number of time frames.

Novel Test Generation Algorithm for Combination Circuits

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

Bridge fault diagnosis using stuck-at fault simulation

A new diagnostic fault simulator is described that diagnoses both feedback and nonfeedback bridge faults in combinational circuits while using information from fault simulation of single stuck-at faults. A realistic fault model is used which considers the existence of the Byzantine Generals problem. Sets representing nodes possibly involved in a defect are partitioned based on logic and fault simulation of failing vectors. The approach has been demonstrated for two-line bridge faults on several large combinational benchmark circuits containing Boolean primitives and has achieved over 98% accuracy for nonfeedback bridge faults and over 85% accuracy for feedback bridge faults with good diagnostic resolution.

NOVEL TEST GENERATION ALGORITHM FOR COMBINATION CIRCUITS

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.

Functional test generation for delay faults in combinational circuits

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

Tests for small gate delay faults in combinational circuits and a test generation method

This paper proposes a method for detecting delay faults of gates in a combinational logic circuit. Assuming that a gate of the circuit has a small delay (a unit delay), the generation of a test for the circuit is described. This paper also describes the generation of the timed seven-valued calculus used in the method. The method has been applied successfully to benchmark circuits having unit delay and a fanout weighted delay. The experimental results show that the method has high fault coverage in all the circuits, and that this can be applied to the detection of gross delay faults. The proposed test method is called the ‘SD test’. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(6): 68–76, 1997

Test for detection and location of intermittent faults in combinational circuits

Faults in combinational circuits are either permanent or intermittent. Intermittent faults tend to be environment-dependent; hence altering the environment might rectify these faults. These faults can be detected by applying random input-vectors (IV). The existence of random intermittent faults might require applying more random IV before detection. The detection of permanent faults requires fewer random IV but correction demands location and replacement of the faulty device, if repair is not feasible. Thus correction of a permanent fault costs more than that of an intermittent fault. The correction cost can be reduced by detecting the type of fault. Since most operational failures in a circuit are due to intermittent faults, it is very important to detect the type of fault in order to find a cheaper solution. This paper discusses the behavior of permanent and intermittent faults in combinational circuits, and introduces a test-detection model (TDM) for these faults. The error latency for an intermittent fault is derived. Two test-strategies are intermixed in the model: random testing for fault-detection, and deterministic testing for deciding on the type of fault. The activity of intermittent faults that requires the minimum number of IV for detection is emphasized. Simulation is used to demonstrate the validity of TDM. Although the variables required in TDM can be difficult to evaluate, estimation of their values is not impossible. A worst-case analysis can always be adopted, where variables are easily evaluated, to find an upper bound on the error latency; thus detection of an intermittent fault is assured with a very high probability. The cost-saving offered by intermittent-fault corrections shows the practical aspect of TDM.

IDDQ Detectable Bridges in Combinational CMOS Circuits

Undetectable stuck-at faults in combinational circuits are related to the existence of logic redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging faults to become undetectable by IDDQ testing. An efficient method for the identification and removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits is presented. OBDD graphs are used to identify the functional equivalence of candidate to f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to improve bridging fault testability, is also proposed. The efficiency of the identification and removal of f-redundancy has been evaluated on a set of benchmark circuits.

Statistical analysis of multiple intermittent faults in combinational circuits

Statistical analysis of multiple intermittent faults (SAMIFs) is proposed as a method for estimating the detection probabilities and fault coverage of multiple intermittent faults in combinational circuits. SAMIFs involves the concurrent simulation of multiple intermittent faults and an estimation of the controllability and observability values for each node of the faulty circuit for a given set of input vectors. The controllabilities and observabilities are then used to derive estimates of the fault-detection probabilities and the overall fault coverage. An algorithm for estimating the fault coverage of a pseudo-random test vector set over a set of multiple intermittent faults in a combinational circuit is also proposed. Experimental results obtained from applying the algorithm to a number of benchmark circuits are also presented.

Diagnostic simulation of stuck-at faults in combinational circuits

Two faults are said to be equivalent, with respect to a test set τ, iff they cannot be distinguished by any test in τ. The sizes of the corresponding equivalence classes of faults are used as a basis for comparing the diagnostic capability of two given test sets. A novel algorithm, called “multiway list splitting,” for computing the Equivalence Classes of stuck-at faults, in combinational (full scan) circuits, with respect to a given test set is presented. Experimental results presented show the algorithm to be more efficient than previously known algorithms based on decision diagrams and diagnosibility matrix.

Simulation and generation of IDDQ tests for bridging faults in combinational circuits

In the absence of information about the layout, test generation and fault simulation systems must target all bridging faults. A novel algorithm, that is both time and space efficient, for simulating I/sub DDQ/ tests for all two-line bridging faults in combinational circuits is presented. Simulation results using randomly generated test sets point to the computational feasibility of targeting all two-line bridging faults. On a more theoretical note, we show that the problem of computing I/sub DDQ/ tests for all two-line bridging faults, even in some restricted classes of circuits, is intractable, and, even under some pessimistic assumptions, a complete I/sub DDQ/ test set for all two-line bridging faults also covers all multiple line, single cluster bridging faults.