Fault-tolerant Routing Scheme Research Articles

An expandable and cost-effective data center network

With the rapid growth of data volume, the escalating complexity of data businesses, and the increasing reliance on the Internet for daily life and production, the scale of data centers is constantly expanding. The data center network (DCN) is a bridge connecting large-scale servers in data centers for large-scale distributed computing. How to build a DCN structure that is flexible and cost-effective, while maintaining its topological properties unchanged during network expansion has become a challenging issue. In this paper, we propose an expandable and cost-effective DCN, namely HHCube, which is based on the half hypercube structure. Further, we analyze some characteristics of HHCube, including connectivity, diameter, and bisection bandwidth of the HHCube. We also design an efficient algorithm to find the shortest path between any two distinct nodes and present a fault-tolerant routing scheme to obtain a fault-tolerant path between any two distinct fault-free nodes in HHCube. Meanwhile, we present two local diagnosis algorithms to determine the status of nodes in HHCube under the PMC model and MM* model, respectively. Our results demonstrate that despite the presence of up to 25% faulty nodes in HHCube, both algorithms achieve a correct diagnosis rate exceeding 90%. Finally, we compare HHCube with state-of-the-art DCNs including Fat-Tree, DCell, BCube, Ficonn, and HSDC, and the experimental results indicate that the HHCube is an excellent candidate for constructing expandable and cost-effective DCNs.

RibsNet: A Scalable, High-Performance, and Cost-Effective Two-Layer-Based Cloud Data Center Network Architecture

Today, we witness an unprecedented surge of data traffic due to the explosive growth of smart devices and intelligent applications. Hence, supporting the Data Center Networks (DCNs) infrastructure by accommodating myriads of servers becomes natural and inevitable. This vision can be realized by providing an interconnecting architecture with higher scalability and remarkable capacity while maintaining fault tolerance, minimum latency, and cost and power efficiency. Motivated by this trend, this paper proposes a new network based on dual-centric dubbed RibsNet, which is a symmetric network composed of two layers of switches and dual-port servers. The proposed network enables the servers to establish all kinds of connections (server-switch and server-server), thus enhancing network fault tolerance with high bisection width and maximizing its performance and reliability. RibsNet allows the gradual addition of servers while preserving all its topological properties; it has a stable and low diameter, which does not exceed six regardless of the DCN’s size. Furthermore, an efficient and fault tolerant routing scheme, exclusively designed for this network, is proposed to enhance the routing efficiency and address different types of failures. Theoretical analysis proves that RibsNet strikes a good balance among several connections within the network and brings outstanding gains in terms of incremental scalability, bisection width, and cost and power savings against various cutting-edge DCNs architectures. Simulation results demonstrate RibsNet as a promising structure that outperforms BCube, DCell, HSDC, and FiConn in terms of latency and throughput by approximately 8%, 6%, 7%, and 26%, respectively.

Fault-Tolerant Secure Routing of B H n -Based Data Center Networks

As the core infrastructure of cloud computing, a large scale of the data center networks (DCNs), which consist of millions of servers with high capacity, suffer from node failure such that the reliability is deteriorated. Malicious group could inevitably compromise the quality and reliability of data; thus, how to ensure the security routing of data is an urgent practical problem. As models for large-scale DCNs, it is worth mentioning the balanced hypercube, which is well-known for its strong connectivity, regularity, and a smaller diameter. Each of which makes a balanced hypercube a trustworthy model to deal with data traffic and provides a certain degree of fault-tolerance as well. In this paper, we use the balanced hypercube as a model for the data center networks and design a reliable safety level by referring to different safety levels of related subgraph. This subgraph contains the source and destination nodes, and the shortest feasible paths are located so that the reliable transmission is achieved. Then, we get that the length of fault-tolerant safety routing of data center networks based on balanced hypercube is always no greater than the Hamming distance plus two. Experiment shows that our fault-tolerant security routing scheme is more effective in the same reliable network environment of DCNs.

Insights on critical energy efficiency approaches in internet-of-things application

Internet-of-things (IoT) is one of the proliferated technologies that result in a larger scale of connection among different computational devices. However, establishing such a connection requires a fault-tolerant routing scheme. The existing routing scheme results in communication but does not address various problems directly linked with energy consumption. Cross layer-based scheme and optimization schemes are frequently used scheme for improving the energy efficiency performance in IoT. Therefore, this paper investigates the approaches where cross-layer-based schemes are used to retain energy efficiencies among resource-constrained devices. The paper discusses the effectivity of the approaches used to optimize network performance in IoT applications. The study outcome of this paper showcase that there are various open-end issues, which is required to be addressed effectively in order to improve the performance of application associated with the IoT system.

A fault tolerant routing scheme for advanced metering infrastructure: an approach towards smart grid

The wireless sensor network is gaining significant attention because of its ubiquitous deployability nature. In general, the role of the wireless sensor network is remarkable in smart city applications for data sensing, collecting, and transmitting. Advanced metering infrastructure is an automatic system for the reading of electricity consumption by individual users. The reading of data from meters normally communicated over a wireless medium. Apart from collecting and sensing, routing is one of the major attributes in the AMI network. Successful communication is possible when the link and node are in the proper state. In this paper, we propose a fault-tolerant routing mechanism named Grid Topological Routing scheme to provide an efficient route in case of encountering a faulty path. The simulation shows better performance against the Routing Protocol for Low-Power and Lossy Networks and Ad-Hoc On-Demand Vector algorithm in terms of power consumption and packet delivery ratio. This model is explicitly designed for the smart grid in India.

An automated fault-tolerant route discovery with congestion control using TFRF model for 3D network-on-chips

As one of the principle patterns of communication technology for 3D-integrated circuit (ICs), the 3D-networks-on-chips (3D-NoCs) have lot of attention from scientific research community. 3D-NoCs has been provided as a propitious solution merging the high parallelism of network-on-chip (NoCs) interconnect paradigm with the high-performance and lower interconnect-power of three-dimensional integration circuits. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a triggered fault-free route forwarding model called TFRF for 3D mesh NoCs without requiring any virtual channels (VCs).TFRF is a deadlock-free scheme by adopting a logic-based routing named TFRF guided by a turn activating rule model. The experimental results show that TFRF possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.

A Comparative Study on Automated Fault—Tolerant Route Discovery with Congestion Control Using TFRF Model for 3-D Network-on-Chips

In recent times, with the capaciousness of on-chip cores endorsed over rapid technology scaling, network-on-chips (NoCs) are turning out to be a crucial element of entire system power performance characteristics. 3D-NoCs has been contributed as an auspicious solution merging the high parallelism of NoCs interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional Integrated Circuits (ICs). For the permanent link faults, an impressive mechanism contemplated is the fault-tolerant routing scheme to provide the performance of the 2-D NoCs. In this article, our proposed Triggered Fault-Free Route Forwarding model (TFRF) for 3-D Mesh NoCs without desiring any virtual channels (VCs) is compared with existing approaches with the intention of validating the performance. The experimental results of our proposed TFRF is evaluated and the performance is enhanced in terms of reliability with minimized overhead and the analytical phase details of the evaluation outcomes.

FL-RuNS: A High-Performance and Runtime Reconfigurable Fault-Tolerant Routing Scheme for Partially Connected Three-Dimensional Networks on Chip

Three-dimensional networks on chip (3D-NoCs) have been proposed as an enormously scalable solution to address communication problems in modern systems on chip. Through-silicon via (TSV) is usually adopted as a viable technology enabling vertical connection among NoC layers. However, TSV-based architectures typically exhibit high vulnerability to transient and permanent faults caused by aging effects, thermal violations, manufacturing issues, or even transient fault sources. Therefore, TSV-based architectures call for robust routing schemes capable of sustaining operation under unpredictable failure patterns. In this paper, we introduce FL-RuNS, a fault-tolerant routing scheme for achieving 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. The proposed scheme uses the concept of vertical link announcement to inform nodes in the network of the health condition of vertical links. This mechanism is able to dynamically and progressively reconfigure the entire network without any packet loss. FL-RuNS requires a very low number of asymmetric virtual channels to achieve both deadlock freedom and reachability. Also, FL-RuNS introduces one-flit-dedicated virtual channels, which are used as an escape buffer in case of TSVs failures. The experimental results have confirmed that FL-RuNS shows better reliability when compared to the recently proposed fault-tolerant routing algorithm. Furthermore, the hardware synthesis performed using a commercial 28-nm technology library shows a reasonable area and power overhead with respect to the non-fault-tolerant baseline.

A Fault-Tolerant Deflection Routing for Network-on-Chip

Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.

LOFT: A low-overhead fault-tolerant routing scheme for 3D NoCs

As one of the main trends of communication technology for 3D integrated circuits, the 3D networks-on-chip (NoCs) have drawn high concern from the academia. The links are main components of the NoCs. For the permanent link faults, the fault-tolerant routing scheme has been regarded as an effective mechanism to ensure the performance of the 2D NoCs. In this paper, we propose a low-overhead fault-tolerant routing scheme called LOFT for 3D Mesh NoCs without requiring any virtual channels (VCs). LOFT is a deadlock-free scheme by adopting a logic-based routing named LBDRe2 guided by a turn model Complete-OE. The experimental results show that LOFT possesses better performance, improved reliability and lower overhead compared with the state-of-the-art reliable routing schemes.

Fault-Tolerant Routing Scheme Based on Leach for Wireless Sensor Networks

Fault-Tolerant Routing Scheme Based on Leach for Wireless Sensor Networks

Dynamic fault‐tolerant routing algorithm for networks‐on‐chip based on localised detouring paths

Downscaled complementary metal-oxide semiconductor (CMOS) technology feature sizes have enabled massive transistor integration densities. Multi-core chips with billions of transistors are now a reality. However, this rapid increase in on-chip resources has come at the expense of higher susceptibility to defects and wear-out. The inter-router communication links of networks-on-chips (NoCs) are composed of metal wires that are especially vulnerable to catastrophic physical effects such as those of electro-migration, which can even cause link disconnects. To address this hazard, fault-tolerant (FT) routing algorithms sustain on-chip communication by re-routing messages around faulty links, or regions. This work presents a new FT routing scheme that employs a localised re-routing approach. Packets are de-toured around faulty links/regions based on purely local and distributed decisions, and without any global link state knowledge. The algorithm, which is proven to be deadlock- and livelock-free, also handles dynamically occurring faults. Detailed evaluation with synthetic traffic patterns and real applications within a full-system simulation environment demonstrate the efficacy of the new scheme with up to 12% of NoC links being faulty. Synthesis results also prove the feasibility of the proposed protocol at modest hardware and power consumption overheads of only over 5 and 2.5%, respectively.

Fault-tolerant compact routing schemes for general graphs

This paper considers compact fault-tolerant routing schemes for weighted general graphs, namely, routing schemes that avoid a set of failed (or forbidden) edges. We present a compact routing scheme capable of handling multiple edge failures. Assume a source node s contains a message M designated to a destination target t and assume a set F of edges crashes (unknown to s). Our scheme routes the message to t (provided that s and t are still connected in G∖F) over a path whose length is proportional to the distance between s and t in G∖F, to |F|3 and to some poly-log factor. The routing table required at a node v is of size proportional to the degree of v in G and some poly-log factor. This improves on the previously known fault-tolerant compact routing scheme for general graphs, which was capable of overcoming at most 2 edge failures.

A Study on Fault Model and Fault-Tolerant Routing for Sensor Networks

Wireless sensor networks require energy-efficient and robust routingprotocols. Most routing protocols for sensor networks try to extendnetwork lifetime by minimizing the energy consumption, but have not taken the network reliability into account. In this paper, we analyze the fault models and propose an ENergy-aware FAult-tolerantRouting scheme, termed as ENFAR. Firstly a link-based uniform fault model is presented, and we adopt a cross-layer design to measurethe transmission delay so as to detect the failed nodes.

Fault-Tolerant Energy-Efficient Priority-Based Routing Scheme for the Multisink Healthcare Sensor Networks

Wireless sensor networks (WSNs) are widely used in battle fields, logistic applications, healthcare, habitat monitoring, environmental monitoring, home security, and variety of other areas. The existing routing algorithms focus on the delivery of data packets to the sink using the shortest path; however, calculating the shortest path is not a cost-effective solution while disseminating datasets of interest to the nearest sink node. The approach presented in this paper extends the existing PBR (priority-based routing) protocol by providing a new fault-tolerant multipath priority-based routing (FT-MPPBR) scheme, which not only balances the energy consumption while selecting multiple paths but also balances the workload of the node closest to the sink. The nodes closer to the sink dissipate more energy and can become the source of a communication bottleneck. Simulation results for the proposed routing scheme are encouraging and clearly show that the FT-MPPBR has outperformed the existing PBR schemes in terms of prolonging the network lifetime and reliability. In healthcare sensor networks, timely dissemination of datasets is critical for the well-being of a patient. This research further extends the PBR architecture for supporting computational intensive analysis by transferring datasets of interest to the sensor grid node for improved communication and better throughput.

NARCO: Neighbor Aware Turn Model-Based Fault Tolerant Routing for NoCs

Network-on-chip (NoC) communication architectures are increasingly being used today to interconnect cores on-chip multiprocessor (CMP) based embedded systems. Permanent faults in NoCs due to fabrication challenges in sub-65 nm CMOS technologies and due to wearout underscore the need for fault tolerant design. In this letter, we propose a novel low-overhead neighbor aware, turn model based fault tolerant routing scheme (NARCO) for NoCs which combines threshold-based replication in network interfaces, a parameterizable region-based neighbor awareness in routers, and the odd-even and inverted odd-even turn models. The proposed scheme enables better packet arrival rate than state of the art, while enabling a tradeoff between communication reliability and energy overhead.

Compiler directed network-on-chip reliability enhancement for chip multiprocessors

Chip multiprocessors (CMPs) are expected to be the building blocks for future computer systems. While architecting these emerging CMPs is a challenging problem on its own, programming them is even more challenging. As the number of cores accommodated in chip multiprocessors increases, network-on-chip (NoC) type communication fabrics are expected to replace traditional point-to-point buses. Most of the prior software related work so far targeting CMPs focus on performance and power aspects. However, as technology scales, components of a CMP are being increasingly exposed to both transient and permanent hardware failures. This paper presents and evaluates a compiler-directed power-performance aware reliability enhancement scheme for network-on-chip (NoC) based chip multiprocessors (CMPs). The proposed scheme improves on-chip communication reliability by duplicating messages traveling across CMP nodes such that, for each original message, its duplicate uses a different set of communication links as much as possible (to satisfy performance constraint). In addition, our approach tries to reuse communication links across the different phases of the program to maximize link shutdown opportunities for the NoC (to satisfy power constraint). Our results show that the proposed approach is very effective in improving on-chip network reliability, without causing excessive power or performance degradation. In our experiments, we also evaluate the performance oriented and energy oriented versions of our compiler-directed reliability enhancement scheme, and compare it to two pure hardware based fault tolerant routing schemes.

Fault-tolerant routing in adversarial mobile ad hoc networks: an efficient route estimation scheme for non-stationary environments

Designing routing schemes that would successfully operate in the presence of adversarial environments in Mobile Ad Hoc Networks (MANETs) is a challenging issue. In this paper, we discuss fault-tolerant routing schemes operating in a network with malfunctioning nodes. Most existing MANET protocols were postulated considering scenarios where all the mobile nodes in the ad hoc network function properly, and in an idealistic manner. However, adversarial environments are common in MANET environments, and misbehaving nodes certainly degrade the performance of these routing protocols. The need for fault tolerant routing protocols was identified to address routing in adversarial environments in the presence of faulty nodes by exploring redundancy-based strategies in networks. It turns out that since the nodes are mobile, the random variables encountered are non-stationary, implying that estimation methods for stationary variables are inadequate. Consequently, in this paper, we present a new fault-tolerant routing scheme that invokes a stochastic learning-based weak estimation procedure to enhance a route estimation phase, which, in turn, is then incorporated in a route selection phase. We are not aware of any reported method that utilizes non-traditional estimates to achieve the ranking of the possible paths. The scheme, which has been rigorously tested by simulation, has been shown to be superior to the existing algorithms.

Practical Deadlock-Free Fault-Tolerant Routing in Meshes Based on the Planar Network Fault Model

The number of virtual channels required for deadlock-free routing is important for cost-effective and high-performance system design. The planar adaptive routing scheme is an effective deadlock avoidance technique using only three virtual channels for each physical channel in 3D or higher dimensional mesh networks with a very simple deadlock avoidance scheme. However, there exist one idle virtual channel for all physical channels along the first dimension and two idle virtual channels for channels along the last dimension in a mesh network based on the planar adaptive routing algorithm. A new deadlock avoidance technique is proposed for 3D meshes using only two virtual channels by making full use of the idle channels. The deadlock-free adaptive routing scheme is then modified to a deadlock-free adaptive fault-tolerant routing scheme based on a planar network (PN) fault model. The proposed deadlock-free adaptive routing scheme is also extended to n-dimensional meshes still using two virtual channels. Sufficient simulation results are presented to demonstrate the effectiveness of the proposed algorithm.

Efficient parallel processing with spin-wave nanoarchitectures

In this paper, we study the algorithm design aspects of three newly developed spin-wave architectures. The architectures are capable of simultaneously transmitting multiple signals using different frequencies, and allow for concurrent read/write operations. Using such features, we show a number of parallel and fault-tolerant routing schemes and introduce a set of generic parallel processing techniques that can be used for design of fast algorithms on these spin-wave architectures. We also present a set of application examples to illustrate the operation of the proposed generic parallel techniques.