Fault-tolerant Routing Algorithm Research Articles

Disjoint Paths Construction and Fault-Tolerant Routing in BCube of Data Center Networks

BCube is a promising structure of data center network, as it can significantly improve the performance of typical applications. With the expansion of network scale and increasement of complexity, reliability and stability of networks have become more essential. In this paper, we study the fault-tolerant routings in BCube. Firstly, we design a fault-tolerant routing algorithm based on node disjoint multi-paths. The proposed multi-path routing has stronger fault tolerance, since each path has no other common nodes except the source node and the destination node. Secondly, we investigate an effective fault-tolerant routing based on routing capabilities algorithm for BCube. The proposed algorithm has higher fault tolerance and success rate of finding feasible routes, since it does not limit the faults number. Thirdly, we present an adaptive path finding algorithm for establishing virtual links between any two nodes in BCube, which can shorten the diameter of BCube. Extensive simulation results show that the proposed routing scheme outperforms the existing popular algorithms. Compared with the state-of-the-art fault-tolerant routing algorithms, the proposed algorithm has a 21.5% to 25.3% improvement on both throughput and packet arrival rate. Meanwhile, it reduces the average latency of 18.6% and the maximum latency of 23.7% in networks.

An Overview on On-chip Network Routing Optimisation

As the number of cores in multi-core systems increases, bus-based systems face significant challenges in terms of scalability, average transmission latency and power consumption. In this context, on-chip networks emerged as a suitable communication architecture for System On Chip (SoC) based entirely on the communication ideas in computer networks and taking into account the characteristics of the system on chip in SoCs. With the introduction of on-chip networks, related research has been developed, such as on-chip network topology, communication quality of service, on-chip network routing algorithms, and on-chip network fault tolerance. He then introduces on-chip network routing algorithms and fault-tolerant routing algorithms from different perspectives, and finally points out the directions of fault-tolerant routing algorithms worthy of research.

E-ReInForMIF Routing Algorithm Based on Energy Selection and Erasure Code Tolerance Machine

Aiming at the problems of data loss and uneven energy consumption in wireless sensor networks during data transmission, this paper proposes a ReInForM transmission fault-tolerant routing algorithm based on energy selection and erasure code fault-tolerant machines (E-ReInForMIF). The E-ReInForMIF algorithm improves the multi-path routing algorithm by combining an erasure coding fault-tolerant machine and node residual energy sorting selection. First, the erasure coding fault-tolerant machine is used to encode the signal, determine the number of transmission paths through multi-path routing, and then select the specific node of the next hop by sorting the residual energy of the node. The E-ReInForMIF routing algorithm effectively solves the problems of uneven energy consumption and data loss in data transmission, improving network lifespan and transmission reliability. Finally, the signal is decoded. The simulation results show that the E-ReInForMIF routing algorithm is superior to the ReInForM routing algorithm in improving the reliability of data transmission.

Dynamic detection of wireless interface faults and fault-tolerant routing algorithm in WiNoC

Wireless network-on-chip (WiNoC) face serious reliability challenges, and the fault-tolerant design of wireless routers (WRs) has a significant impact on the transmission efficiency of the overall on-chip network. Due to the continuous shrinking of CMOS technology and the integration of wireless technology in complex circuits, WRs appear to become more prevalent. In this paper, we propose a dynamic detection strategy for wireless interface faults in WiNoC, which classifies the fault scenarios of wireless interfaces in WRs, implements wireless interface fault detection in WiNoC operation, and updates the fault scenarios. Meanwhile, a fault-free WR table-based nearest route algorithm is also presented to maximize the network performance. The Evaluations show that the proposed scheme can effectively guarantee the network performance when WR faults occur in the network and is also effective under the case of moderate WR fault rate.

Fault-Tolerant Routing With Load Balancing in LeTQ Networks

With the increasing scale of parallel computer interconnection network, the possibility of processor failure or link failure between processors in the network is also increasing. In the design of supercomputers, not only link overhead and communication delay should be taken into account, but also fault-tolerant performance of networks should be emphasized. Locally exchanged twisted cube ( <inline-formula><tex-math notation="LaTeX">$LeTQ$</tex-math></inline-formula> ) is a newly proposed interconnection network with lower link overhead and shorter diameter. With the increasing scale of supercomputers, fault-tolerant routing is indispensable. In this article, we propose a new load balancing fault-tolerant routing algorithm based on node contraction for <inline-formula><tex-math notation="LaTeX">$LeTQ$</tex-math></inline-formula> networks. The proposed algorithm uses the node shrinkage method to evaluate the priority of nodes. The sending node adaptively adjusts the probability of forwarding packets to the neighbor node according to the priority of the neighbor node and the state of the network. The path can be adapted to the load state of the network. The simulation results show that the fault-tolerant routing algorithm has good performance in throughput and delay.

BCCC Disjoint Path Construction Algorithm and Fault-Tolerant Routing Algorithm under Restricted Connectivity

Connectivity in large-scale data center networks is a critical indicator to evaluate network state. A feasible and performance-guaranteed algorithm enables us to find disjoint paths between network vertices to ensure effective data transfer and to maintain the normal operation of network in case of faulty nodes. As an important data center network, BCube Connected Crossbars (BCCC) has many excellent properties that have been widely studied. In this paper, we first propose a vertex disjoint path algorithm with the time complexity of O(nk) in BCCC, where n denotes a switch connected to n servers and k denotes dimension. Then, we prove that the restricted connectivity of BCCC(n,k). Finally, we present an O(knκ1(G)) fault-free algorithm in BCCC, where κ1(G) is the restricted connectivity. This algorithm can obtain a fault-free path between any two distinct fault-free vertices under the condition that each vertex has at least one fault-free neighbor in the BCCC and a set of faulty vertices F with |F|&lt;κ1(G).

Fault-Tolerant Secure Routing Based on Trust Evaluation Model in Data Center Networks

With the rise of cloud computing technology, the whole information technology industry has undergone dramatic changes. Large-scale computing and the growing demand for computing power from large data have made it impossible for traditional data center network topology construction methods and network layer operation control methods with good stability to meet the requirements of technological development. The topology of a data center network is usually characterized as an undirected graph, and graph algorithms are used to implement communication patterns in complex network structures. However, the routing algorithms proposed earlier for graphs cannot be applied to all topological graphs. Based on the comprehensive interactive trust evaluation network security model, this study analyzes the advantages and disadvantages of relevant algorithms and proposes a fault-tolerant routing algorithm suitable for all networks. The algorithm can dynamically call different algorithms according to the number of current nodes and links. From the simulation results, it can be found that the algorithm not only improves the accuracy and fault tolerance but also effectively reduces the loss of time and memory.

Independent spanning trees in Eisenstein–Jacobi networks

Spanning trees are widely used in interconnection networks for routing, broadcasting, fault-tolerance, and securely delivering messages, as well as parallel and distributed computing. The problem of efficiently finding a maximal set of independent spanning trees (ISTs) is still open for arbitrary (general) interconnection topologies (graphs). The first contribution of this paper is presenting two efficient methods that solve the problem in Eisenstein–Jacobi (EJ) networks. The first constructs three Edge-Disjoint Node-Independent Spanning Trees (EDNISTs), whereas the second constructs six ISTs but not edge disjoint. Both constructions have time complexity O(n), where n is the number of nodes. The second contribution is providing a distributed fault-tolerant routing algorithm based on the constructed trees with time complexity O(1) and communication complexity O(|P|), where P is the routing path. The experimental results measure the maximum and the average of all maximum number of communication steps between the root node and all other nodes among all ISTs with the consideration of all possible faulty nodes. In addition, the comparison shows that the proposed method outperforms the state-of-the-art method in broadcasting in terms of node coverage in the presence of failures.

Reinforcement Learning Based Fault-Tolerant Routing Algorithm for Mesh Based NoC and Its FPGA Implementation

Network-on-Chip (NoC) has emerged as the most promising on-chip interconnection framework in Multi-Processor System-on-Chips (MPSoCs) due to its efficiency and scalability. In the deep sub-micron level, NoCs are vulnerable to faults, which leads to the failure of network components such as links and routers. Failures in NoC components diminish system efficiency and reliability. This paper proposes a Reinforcement Learning based Fault-Tolerant Routing (RL-FTR) algorithm to tackle the routing issues caused by link and router faults in the mesh-based NoC architecture. The efficiency of the proposed RL-FTR algorithm is examined using System-C based cycle-accurate NoC simulator. Simulations are carried out by increasing the number of links and router faults in various sizes of mesh. Followed by simulations, real-time functioning of the proposed RL-FTR algorithm is observed using the FPGA implementation. Results of the simulation and hardware shows that the proposed RL-FTR algorithm provides an optimal routing path from the source router to the destination router.

Fault-tolerant routing algorithm based on disjoint paths in 3-ary n-cube networks with structure faults

The 3-ary n-cube network is widely used in large-scale multi-processor parallel computers. It is an important issue to design high-performance communication technology with fault tolerance. In this paper, we study the fault-tolerant routing of 3-ary n-cube without desired intersection. Firstly, we propose a fully adaptive routing algorithm for 3-ary n-cube network based on the new virtual network partition technology. The virtual channel allocation of the algorithm is given and its deadlock free property is proved. Secondly, we propose a construction of disjoint paths in 3-ary n-cube networks under the fault model. Finally, we propose a novel fault-tolerant routing algorithm for 3-ary n-cube networks based on the disjoint path with structure faults. The simulation results show that the proposed fault-tolerant routing algorithm outperforms the previous fault-tolerant routing algorithm in many situations, which has a 19–21 percent increase in throughput and the injection rate.

Link Fault Tolerant Routing Algorithms in Mirrored K-Ary N-Tree Interconnection Networks

This paper investigates the fault tolerance of Mirrored k-Ary n-Tree (MiKANT) networks with link faulty. The MiKANT network is a variant of the traditional k-ary n-tree (Fat-tree) and Clos networks. It doubles the number of compute nodes of the fat-tree by adding a few switches and links and has a shorter average distance to reduce the packet latency. As the scale of MiKANT becomes larger, the probability of link faulty becomes higher. In order to improve the successful routing ratio of MiKANT, we give four link fault tolerant routing algorithms for MiKANT and evaluate their performance through simulations. In addition, the performance of the combined algorithms is also evaluated.

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

Criso: An Incremental Scalable and Cost-Effective Network Architecture for Data Centers

With the explosive data growth, an enormous number of computing and networking components (e.g., servers, switches, and wires) are continuously being augmented to data centers. Data center networks (DCNs) - maintaining a high network capacity - must be cost efficient, incrementally scalable, and fault-tolerant. To address these challenges, we propose in this study a new type of DCN architecture referred to as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> . Different from the existing network architectures, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> is designed hierarchically and recursively by employing two ports servers and commodity switches. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> is constructed based on numerous isomorphic <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pod</i> s, each of which leverages external interfaces supplied by switches to connect with neighboring pods. Additionally, a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pod</i> -based and fault-tolerant routing algorithm is designed to handle multiple failures. <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> has an array of promising features, including being cost-efficient and delivering a high-network capacity that can be extended to millions of nodes. The analytic results demonstrate that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> is significantly superior to the four state-of-the-art data center structures in terms of network capacity, scalability, cost, power consumption, and other static characteristics. Furthermore, the experimental results unveil that <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> satisfies the fault-tolerant demands of modern data centers. Compared to the four existing topologies (i.e., <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DCell</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BCube</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">FiConn</i> , <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Fat-Tree</i> ) that have been widely investigated, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Criso</i> is adroit at maintaining a balanced performance in terms of throughput and latency.

Aggressive Fine-Grained Power Gating of NoC Buffers

Power gating is effective for networks-on-chip (NoCs) to reduce the excessive leakage power dissipated by idle network components. Most existing NoC power-gating approaches rely on the routing algorithms to mitigate the power-gating blocking latency problem. When the network becomes faulty and fault-tolerant routing algorithms are applied, these approaches are no longer applicable or can seriously degrade the performance. Other approaches propose fine-grained buffer power gating, but they are too conservative in power saving due to the buffer backpressure flow control. To address these problems, we propose an aggressive fine-grained power gating of flit-sized buffer entries by adopting backpressureless flow control in an input-buffered network. The power-gating decisions are made based on the flit deflection rate. However, directly applying the backpressureless flow control leads to the difficulties of multiflit packet truncation and protocol deadlocks. Therefore, we modify the packet injection architecture to avoid packet truncation. This is done by chaining the local input port with a randomly chosen input port. Finally, we design a progressive recovery framework to handle both livelocks and protocol deadlocks. It does not need to truncate packets or strictly separate different message classes when the network is free of livelocks or protocol deadlocks. The experimental results show that with a hardware overhead of 9.6%, our design can save up to 59% network power consumption in both a fault-free and a faulty NoC with little zero-load latency penalty. Our design also approaches an ideal energy-proportional NoC because it can constantly reduce power consumption over a wide range of injection rates.

A Dynamic Sufficient Condition of Deadlock-Freedom for High-Performance Fault-Tolerant Routing in Networks-on-Chips

Networks-on-Chips (NoCs) are considered to be the paradigm of choice for on-chip communication and are today widely adopted in many-core systems. Many existing routing solutions make use of virtual channels (VCs) to avoid deadlocks while offering enough routing flexibility to avoid faulty and congested areas in a NoC. However, most of the current solutions rely on an overly restrictive, static partitioning of VCs, which results in an underutilization of their throughput enhancement capabilities. To overcome the limitations of such approaches, we introduce a new sufficient condition of deadlock-freedom that greatly relaxes the restrictions imposed by the classic VC-based deadlock-avoidance methods. The strength of our condition lies in the fact that it is imposed on packets at runtime and does not require any partitioning of virtual channels, which makes it possible to fully exploit them to reduce packet blocking and boost performance. Based on this condition, we present a generic, topology-agnostic routing algorithm design methodology that can be used to construct highly flexible routing algorithms in only a few steps. Several examples are presented to showcase the usefulness of our approach for the construction of fault-tolerant routing algorithms, as well as the enhancement and the proof of existing routing algorithms. The implementation of all the required mechanisms in hardware is also described in detail, thereby demonstrating its feasibility in an on-chip environment.

A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs

Scalability is a significant issue in system-on-a-chip architectures because of the rapid increase in numerous on-chip resources. Moreover, hybrid processing elements demand diverse communication requirements, which system-on-a-chip architectures are unable to handle gracefully. Network-on-a-chip architectures have been proposed to address the scalability, contention, reusability, and congestion-related problems of current system-on-a-chip architectures. The reliability appears to be a challenging aspect of network-on-a-chip architectures because of the physical faults introduced in post-manufacturing processes. Therefore, to overcome such failures in network-on-a-chip architectures, fault-tolerant routing is critical. In this article, a network adaptive fault-tolerant routing algorithm is proposed, where the proposed algorithm enhances an efficient dynamic and adaptive routing algorithm. The proposed algorithm avoids livelocks because of its ability to select an alternate outport. It also manages to bypass congested regions of the network and balances the traffic load between outports that have an equal number of hop counts to its destination. Simulation results verified that in a fault-free scenario, the proposed solution outperformed a fault-tolerant XY by achieving a lower latency. At the same time, it attained a higher flit delivery ratio compared to the efficient dynamic and adaptive routing algorithm. Meanwhile, in the situation of a faulty network, the proposed algorithm could reach a higher flit delivery ratio of up to 18% while still consuming less power compared to the efficient dynamic and adaptive routing algorithm.

Fault-Tolerant Routing Mechanism in 3D Optical Network-on-Chip Based on Node Reuse

The three-dimensional Network-on-Chips (3D NoCs) has become a mature multi-core interconnection architecture in recent years. However, the traditional electrical lines have very limited bandwidth and high energy consumption, making the photonic interconnection promising for future 3D Optical NoCs (ONoCs). Since existing solutions cannot well guarantee the fault-tolerant ability of 3D ONoCs, in this paper, we propose a reliable optical router (OR) structure which sacrifices less redundancy to obtain more restore paths. Moreover, by using our fault-tolerant routing algorithm, the restore path can be found inside the disabled OR under the deadlock-free condition, i.e., fault-node reuse. Experimental results show that the proposed approach outperforms the previous related works by maximum 81.1 percent and 33.0 percent on average for throughput performance under different synthetic and real traffic patterns. It can improve the system average optical signal to noise ratio (OSNR) performance by maximum 26.92 percent and 12.57 percent on average, and it can improve the average energy consumption performance by 0.3 percent to 15.2 percent under different topology types/sizes, failure rates, OR structures, and payload packet sizes.

True Event-Driven and Fault-Tolerant Routing in Wireless Sensor Network

Low-cost sensor nodes being prone to fault, disambiguation between the fault and the event is challenging in event-driven routing. In this paper, we present a True Event-driven and fault-tolerant routing algorithm that sends report to the base station through multi-hops when any node confirms environmental event such as wildfire, earthquake, high chemical density etc. Here, true events and faulty measurements are disambiguated using the majority voting algorithm. Faulty measurements are ignored, but in case of true-event, an alert message is routed to the Base Station through multi hops using our routing algorithm. In our routing algorithm a multi objective weighted sum method and hop-count is utilized to select the most suitable node from neighbors to relay event report towards the Base Station bypassing hole/void area in the network. We simulated our proposed method using network simulator NS-2.35 and compared with the existing routing algorithm using performance metrics namely packet error rate, latency, and network lifetime. We also evaluated our event detection algorithm using performance metrics namely, false alarm rate, and event node detection accuracy. Simulation results showed that our proposed method outperforms the baseline algorithm.

ADFT: an adaptive, distributed, fault-tolerant routing algorithm for 3D mesh-based networks-on-chip

Nowadays, three-dimensional network-on-chips (3D-NoCs) have been introduced as the most efficient communication architectures. In these architectures, it is likely to encounter some faults. Therefore, an important goal in designing such architectures is to make them more tolerable against faults. In this paper, an adaptive, distributed and fault-tolerant routing algorithm called ADFT is proposed for 3D mesh-based NoC that is able to tolerate permanent faults and does not require any additional circuit for fault-tolerant. In order to evaluate the performance of the ADFT, we compared it with LOFT in terms of latency and throughput. Simulation results show improvement of the proposed method.

ADFT: An Adaptive, Distributed, Fault-Tolerant Routing Algorithm for 3D Mesh-Based Networks-on-Chip

Nowadays, three-dimensional network-on-chips (3D-NoCs) have been introduced as the most efficient communication architectures. In these architectures, it is likely to encounter some faults. Therefore, an important goal in designing such architectures is to make them more tolerable against faults. In this paper, an adaptive, distributed and fault-tolerant routing algorithm called ADFT is proposed for 3D mesh-based NoC that is able to tolerate permanent faults and does not require any additional circuit for fault-tolerant. In order to evaluate the performance of the ADFT, we compared it with LOFT in terms of latency and throughput. Simulation results show improvement of the proposed method.