Fault-tolerant NoCs Research Articles

BiSuT: A NoC-Based Bit-Shuffling Technique for Multiple Permanent Faults Mitigation

Since several decades, fault tolerance has become a major research field due to transistor shrinking and core number increasing in system-on-chip (SoC). Especially, faults occurring to the network-on-chips (NoCs) of those systems have a significant impact, due to the high amount of data, crossing the NoC, for the communication among intellectual properties (IPs). Furthermore, existing fault-tolerant approaches cannot efficiently deal with several permanent faults, which occur in NoC routers. To address these limitations, we propose the bit shuffling method (BiSuT) for fault-tolerant NoCs that reduces the impact of faults on data communications. To achieve that, the proposed approach exploits, at runtime, the position of permanent faults and changes the order of bits inside a flit. Our method reduces, as much as possible, the impact of faults by transferring the faults on least significant bits (LSBs), instead of keeping them on most significant bits (MSBs). The results obtained by extensive evaluations show that BiSuT can reduce the impact of multiple permanent faults, with low hardware costs, compared to the existing approaches, like the Hamming code.

An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

Fault-Tolerant Application-Specific Topology-Based NoC and Its Prototype on an FPGA

Application-Specific Networks-on-Chips (ASNoCs) are suitable communication platforms for meeting current application requirements. Interconnection links are the primary components involved in communication between the cores of an ASNoC design. The integration density in ASNoC increases with continuous scaling down of the transistor size. Excessive integration density in ASNoC can result in the formation of thermal hotspots, which can cause a system to fail permanently. As a result, fault-tolerant techniques are required to address the permanent faults in interconnection links of an ASNoC design. By taking into account link faults in the topology, this paper introduces a fault-tolerant application-specific topology-based NoC design and its prototype on an FPGA. To place spare links in the ASNoC topology, a meta-heuristic algorithm based on Particle Swarm Optimization (PSO) is proposed. By taking link faults into account in ASNoC design, we also propose an application mapping heuristic and a table-based fault-tolerant routing algorithm. Experiments are carried out for a specific link and any link fault in fault-tolerant topologies generated by our approach and approaches reported in the literature. For the experimentation, we used the multi-media applications Picture-in-Picture (PiP), Moving Pictures Expert Group (MPEG) - 4, MP3Encoder, and Video Object Plane Decoder (VOPD). Experiments are run on software and hardware platforms. The static performance metric communication cost and the dynamic performance metrics network latency, throughput, and router power consumption are examined using software platform. In the hardware platform, the Field Programmable Gate Array (FPGA) is used to validate proposed fault-tolerant topologies and analyze performance metrics such as application runtime, resource utilization, and power consumption. The results are compared with the existing approaches, specifically Ring topology and its modified versions on both software and hardware platforms. The experimental results obtained from software and hardware platforms for a specific link and any link fault show significant improvements in performance metrics using our approach when compared with the related works in the literature.

Fully Reliable Dynamic Routing Logic for a Fault-Tolerant NoC Architecture

A fault-tolerant adaptive wormhole routing function for Networks-on-Chips (NoCs) is presented. The novelty of this routing logic is that it is capable of using runtime information on availability of links to dynamically bypass faulty channels. When faults occur, no offline reconfiguration or dropping of packets is necessary. Instead, dynamic routes are suggested on-the-fly. Routing decisions are based only on local knowledge, which allows for fast switching. Our approach does not use any costly virtual channels. As we do not prohibit cyclic dependencies, the routing function provides minimal routing from source to destination even in the presence of faults. We have implemented the architecture design using synthesizable HDL. Using simulations, we have assessed the overhead of our approach in terms of latency, power and area. On average, even with 40% of the links faulty our routing logic is capable performing correctly. Using formal verification, we have proven 100% reliability up to three faults, i.e., for any combination of three faults our routing logic remains connected, deadlock-free and livelock-free.

Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs

We study the ultimate limits of hardware solutions for the self-protection strategies against permanent faults in networks on chips (NoCs). NoCs reliability is improved by replacing each base router by an augmented router which includes extra protection circuitry. We compare the protection achieved by the self-test and self-protect (STAP) architectures to that of triple modular redundancy with voting (TMR). Two STAP architectures are considered. In the first one, a defective router self-disconnects from the network, while it self-heals in the second one. In practice, none of the considered architectures (STAP or TMR) can tolerate all the permanent faults, especially faults in the extra-circuitry for protection or voting, and consequently, there will always be some unidentified defective augmented routers which are going to transmit errors in an unpredictable manner. This study consists of tackling this fundamental problem. Specifically, we study and determine the average percentage of <underline>residual</underline> unidentified defective routers (UDRs) and their impact on the overall reliability of the NoC in light of self-protection strategies. Our study shows that TMR is the most efficient solution to limit the average percentage of UDRs when there are typically less than a 0.1 percent of defective base routers. However, TMR is also the most cost prohibitive and the least power efficient. Above 1% of defective base routers, the STAP approaches are more efficient although the protection efficiency decreases inexorably in the very defective technologies (e.g. when there is 10% or more of defective base routers). For instance, if the chip includes 10% of defective base routers, our study shows that there will remain on the average 1% of UDRs, which causes a major challenge for NoC reliability.

An Energy-Efficient NoC Router with Adaptive Fault-Tolerance Using Channel Slicing and On-Demand TMR

The competing goals of energy-efficiency, performance, and fault tolerance have not been well bridged in current NoC designs. In this paper, we propose an energy-efficient NoC router that exhibits strong fault-tolerance by leveraging channel slicing. This router has three identical router slices connected with internal sharing paths. Channel slicing reduces the overhead of applying power gating to improve energy-efficiency. When faults occur in any of the slices, resource sharing is enabled to enhance fault-tolerance. These router slices can also be harnessed for on-demand TMR, to further improve fault-tolerance and reduce the need for deploying costly on-chip testers. Our method can diagnose and repair both control and datapath faults without interrupting normal NoC operations. Experimental results show that our proposed router can tolerate 180 percent more gate faults than the state-of-the-art fault-tolerant NoC router architecture HPR. In addition, 64 percent energy improvement at low injection rate, and 28 percent energy improvement at high injection rate are achieved compared to HPR. Furthermore, our method attains 100 percent higher throughput (with 40 faults in one router) compared to HPR. Our proposed method increases router logic area by 7.8 percent compared to baseline.

Review on Fault-Tolerant NoC Designs

By benefiting from the development of the semiconductor technology, many-core system-on-chips (SoCs) have been widely used in electronic devices. Network-on-chips (NoCs) can address the massive stress of on-chip communications due to the advantages of high bandwidth, low latency, and good flexibility. Since deep sub-micron era, the reliability has become a critical constraint for integrated circuits. To provide correct data transmission, fault-tolerant NoCs have been researched widely in last decades, and many valuable designs have been proposed. This work introduces and summarizes the state-of-the-art technologies for fault diagnosis and fault recovery in fault-tolerant NoCs. Moreover, this work makes prospects for the future's research.

A virtual filter based fast assessment methodology for fault tolerant NoCs

A virtual filter based fast assessment methodology for fault tolerant NoCs

A New BIST-based Test Approach with the Fault Location Capability for Communication Channels in Network-on-Chip

In this paper, a new BIST based test approach to detecting short faults on the communication channels data links in network-on-chip is proposed. The rationale underlying the novelty of the proposed approach is that it is capable of locating the faulty channels while simultaneously performing the testing as well as updating the Routing Tables (RT) in which irregular Mesh-based and fault tolerant NoCs that are using Table-based routing. The proposed approach encompasses TPG and TRA located in the Network Adapter (NA) as well as a Packet Comparing Module (PCM) embedded in the routers. The approach, in addition, with a high scalability leads to 100% Test Coverage (TC) and 82.3% capability of diagnosing faulty channels in NoCs with a high scale. Furthermore, the approach is capable of being performed within one Round (two phase) run with a total time of 70 clocks which is considered as cost-effective compared with the preceding methods. The simulation results demonstrate that the hardware cost of PCM is trivial compared with the hardware of RASoC, HERMES, AEthereal and Vici routers.

Collaborative Routing Algorithm for Fault Tolerance in Network on Chip CRAFT NoC

Many fault tolerance techniques have been proposed in Network on Chip to cope with defects during fabrication or faults during product lifetime. Fault tolerance routing algorithm provide reliable mechanisms for continue delivering their services in spite of defective nodes due to the presence of permanent and/or transient faults throughout their lifetime implementation. This paper presents a new approach in the domain of fault-tolerant NoC with two main contributions. Firstly, we consider a unified fault model that include transient faults, permanent faults and congestion considered as a fault. Secondly, we present a new architecture based on sub-nets and give an overview of the associated test and (re)routing algorithm. The main result of this paper, is a new routing algorithm called Collaborative Routing Algorithm for Fault Tolerance in Network on Chip (CRAFT-NoC). We compare our approach with ACOFAR that considers as well congestion and permanent faults. Our simulation results show significant improvements in terms of both latency and reliability.

Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors

The increasing number of cores on a chip has made the network on chip (NoC) concept the standard communication paradigm for chip multiprocessors. A fault in an NoC leads to undesirable ramifications that can severely impact the performance of a chip. Therefore, it is vital to design fault tolerant NoCs. In this paper, we present Shield , a reliable NoC router architecture that has the unique ability to tolerate both hard and soft errors in the routing pipeline using techniques such as spatial redundancy, exploitation of idle cycles, bypassing of faulty resources and selective hardening. Using Mean Time to Failure and Silicon Protection Factor metrics, we show that Shield is six times more reliable than the baseline-unprotected router and is at least 1.5 times more reliable than existing fault tolerant router architectures. We introduce a new metric called Soft Error Improvement Factor and show that the soft error tolerance of Shield has improved by three times in comparison to the baseline-unprotected router. This reliability improvement is accomplished by incurring an area and power overhead of 34 and 31 percent respectively. Latency analysis using SPLASH-2 and PARSEC reveals that in the presence of faults, latency increases by a modest 13 and 10 percent respectively.

Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures

Network-on-Chips (NoCs) are quickly becoming the standard communication paradigm for the growing number of cores on the chip. While NoCs can deliver sufficient bandwidth and enhance scalability, NoCs suffer from high power consumption due to the router microarchitecture and communication channels that facilitate inter-core communication. As technology keeps scaling down in the nanometer regime, unpredictable device behavior due to aging, infant mortality, design defects, soft errors, aggressive design, and process-voltage-temperature variations, will increase and will result in a significant increase in faults (both permanent and transient) and hardware failures. In this paper, we propose QORE-a fault tolerant NoC architecture with Multi-Function Channel (MFC) buffers. The use of MFC buffers and their associated control (link and fault controllers) enhance fault-tolerance by allowing the NoC to dynamically adapt to faults at the link level and reverse propagation direction to avoid faulty links. Additionally, MFC buffers reduce router power and improve performance by eliminating in-router buffering. We utilize a machine learning technique in our link controllers to predict the direction of traffic flow in order to more efficiently reverse links. Our simulation results using real benchmarks and synthetic traffic mixes show that QORE improves speedup by 1.3x and throughput by 2.3x when compared to state-of-the art fault tolerant NoCs designs such as Ariadne and Vicis. Moreover, using Synopsys Design Compiler, we also show that network power in QORE is reduced by 21 percent with minimal control overhead.

A unified link-layer fault-tolerant architecture for network-based many-core embedded systems

Reliability is an important design concern for modern many-core embedded systems. Specifically, on-chip interconnecting systems are vulnerable to permanent channel faults and transient data transmission faults which may significantly impact the overall system performance. In this work, a Unified Link-layer Fault-tolerant NoC (ULF-NoC) architecture is proposed. ULF-NoC is developed for NoC equipped with bidirectional channels and features wormhole switching (instead of store-and-forward switching) and packet-based retransmission. An intelligent buffer controller is developed that does not require separate, dedicated buffer spaces to support packet retransmissions. Extensive simulations using both synthetic and real world data traffics demonstrated marked performance of the proposed ULF-NoC solution.

Online Reconfigurable Self-Timed Links for Fault Tolerant NoC

We propose link structures for NoC that have properties for tolerating efficiently transient, intermittent, and permanent errors. This is a necessary step to be taken in order to implement reliable systems in future nanoscale technologies. The protection against transient errors is realized using Hamming coding and interleaving for error detection and retransmission as the recovery method. We introduce two approaches for tackling the intermittent and permanent errors. In the first approach, spare wires are introduced together with reconfiguration circuitry. The other approach uses time redundancy, the transmission is split into two parts, where the data is doubled. In both structures the presence of permanent or intermittent errors is monitored by analyzing previous error syndromes. The links are based on self-timed signaling in which the handshake signals are protected using triple modular redundancy. We present the structures, operation, and designs for the different components of the links. The fault tolerance properties are analyzed using a fault model containing temporary, intermittent, and permanent faults that occur both as bursts and as single faults. The results show a considerable enhancement in the fault tolerance at the cost of performance and area, and with only a slight increase in power consumption.