Fault Tolerant Multiplier Research Articles

A novel fault tolerant multiplier using single digit conversion based self checking scheme

Digital multipliers are key component of all digital signal processing applications. Numerous algorithms and architectures have been proposed to design high-speed and self repairable multipliers for critical applications like space craft and medical applications. This work proposes a self checking scheme for fixed-width array multipliers. The proposed scheme verifies multiply operation by single digit conversion based verification, mainly relying on the use of addition called (MVA) multiplication verification algorithm. To tolerate the fault that occurs in the multiplier circuit, redundancy replicas of multiplier modules are used to replace faulty one. Our proposed multiplier has been implemented using synopsis complier tool, which achieve a low-cost fault-tolerant design when compare with conventional redundancy based error tolerant techniques.

Generalised fault-tolerant stored-unibit-transfer residue number system multiplier for moduli set {2 n −1, 2 n , 2 n +1}

Residue number system (RNS) which utilises redundant encoding for the residues is called redundant residue number system (RRNS). It can accelerate multiplication which is a high-latency operation. Using stored-unibit-transfer (SUT) redundant encoding in RRNS called SUT-RNS has been shown as an efficient number system for arithmetic operation. Radix-2h SUT-RNS multiplication has been proposed in previous studies for modulo 2n−1, but it has not been generalised for each moduli lengths (n) and radix (r=2h). Also, SUT-RNS multiplication for modulo 2n+1 has not been discussed. In this study the authors remove these weaknesses by proposing general radix-2h SUT-RNS multiplication for the moduli set {2n−1, 2n, 2n+1}. Moreover, the authors demonstrate that our approach enables a unified design for the moduli set multipliers, which results in designing fault-tolerant SUT-RNS multipliers with low hardware redundancy. Results indicate that the proposed general SUT-RNS multiplier for the moduli set {2n−1, 2n, 2n+1} is a fast fault-tolerant multiplier which outperforms area, power and energy/operation of existing RRNS multiplier.

Design of a robust fault-tolerant multiplier

This paper presents a construction of a robust fault-tolerant multiplier aiming at high safety, where the output does not differ much from the normal value, even if a temporary fault is produced in the operation unit. For this purpose, a robust fault-tolerant divider circuit by a fixed positive constant is devised, which is called divider. The multiplier is constructed by arranging such dividers in parallel. The proposed robust fault-tolerant multiplier is based on the distributed coding, where the input/output information is always represented by the number of pulses. Consequently, a system-down is not produced even if more than one temporary error is generated, which is different from the majority redundant circuit. Another feature is that there is no hardware core, such as the majority-decision circuit for the output signal selection, and a temporary error does not produce a system-down.

Residue arithmetic for a fault-tolerant multiplier: The choice of the best triple of bases

A fault tolerant multiplier is presented and discussed with regards its capability to detect and correct single and double errors. Fault tolerance is achieved by joining two techniques: the introduction of physical redundancy (Triple Modular Redundancy) and the use of an error correcting code based on Residue Number System. In particular, we present criteria allowing the identification of the best set of bases to detect and correct a given number of bits of the considered multiplier and the results obtained.