Fault Tolerant FPGA Research Articles

Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM

This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. The proposed architecture does not require fine-grained fault location, and the error map is stored in non-volatile resistive memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. Significant yield enhancement is expected using this architecture. The architecture has been verified in a test chip fabricated in 28nm technology. Redundancy operation is solely controlled by on chip fault locators which are HfO2-based resistive memories monolithically integrated after CMOS process. The maximum shift in performance is about 2 percent when the redundancy is engaged, and the power footprint is unaffected.

FPGA Based Multiple Fault Tolerant and Recoverable Technique Using Triple Modular Redundancy (FRTMR)

Triple Modular Redundancy (TMR) is real time reliability known to improve computing systems. This paper presents an approach towards the implementation of a fault tolerant FPGA based technique. Proposed scheme allows the diagnosis of transient and permanent fault affecting systems. This technique allows to easily identify whether a fault affects one of the replicated modules or the technique itself and whether such a fault is permanent or transient. The scheme can effectively recover computing systems from single transient fault w/o introducing any re-computing delay; hence, it is suitable for real time applications. Time taken for identification of the fault and recovery is less than 8ns. FPGA based fault injection experiment reveal that, the error detection and recovery coverage of 100% and 90% in the presence of single and two faulty models, respectively.