Fault-tolerant Design Method Research Articles

Review of the Fault-Tolerant Strategy for Space Manipulators With Joint Failure

The fault-tolerant strategy of space manipulator is very important to guarantee the task completion and safety after locked joint failure (LJF) occurs. According to the different research stages, the fault-tolerant strategy of the space manipulator with locked joint failure (SMLJF) is divided into the fault-tolerant strategy in design stage and use stage. In view of the fault-tolerant strategy in the design phase, the system-level design and component-level design are reviewed, the fault-tolerant design methods of the structure and joints of the space manipulator are introduced, and the problems existing in these methods are pointed out. In view of the fault-tolerant strategy in the use phase, it can be divided into fault-tolerant strategy before and after LJF, respectively. The fault-tolerant strategy before LJF such as artificial joint limits, global fault-tolerant path planning, and the fault-tolerant strategy after LJF including online fault-tolerant strategy and offline fault-tolerant strategy is reviewed in detail. The current research status of fault-tolerant strategy for SMLJF is introduced systematically, and the problems of these strategies are also detailly analyzed in this paper. Finally, all the existing problems of fault-tolerant strategy for SMLJF are summarized, and the research direction of fault-tolerant strategy is prospected.

Robust Adaptive Fault-Tolerant Tracking Control for Uncertain Linear Systems With Actuator Failures Based on the Closed-Loop Reference Model

This paper addresses the problem of robust adaptive fault-tolerant tracking control for a class of linear systems with parameter uncertainty, external disturbance, and actuator faults including loss of effectiveness, outage, and stuck. According to the online estimation information provided by adaptive mechanism, a fault-tolerant compensation controller is constructed for robust tracking of closed-loop reference model systems. Compared with the existing results, by introducing the closed loop reference model which provides the additional degree-of-freedom, the transient performance of the systems can be improved. It is shown that the signals of the resulting adaptive closed-loop systems are bounded and the tracking error converges to zero asymptotically. A simulation example is provided to verify the effectiveness of the proposed fault-tolerant design method.

Sensor-Fault-Estimation-Based Tolerant Control for Single-Phase Two-Level PWM Rectifier in Electric Traction System

This article presents a fault-estimation-based tolerant control strategy for single-phase two-level pulsewidth modulation rectifier subjected to catenary current sensor fault and dc-link voltage sensor fault. First, an augmented descriptor system is developed for the rectifier, whose augmented state vector consists of the state vector of original system as well as the sensor fault together with the measurement disturbance. Then, a linear reduced-order observer is designed for the descriptor plant. Accurate asymptotic estimation of the original state vector and the disturbed sensor fault are thus achieved simultaneously. Finally, the fault tolerant design method is addressed through sensor fault compensation, which allows the pre-design controller to continue to function normally even when both catenary current sensor and dc-link voltage sensor are faulty. Simulation and hardware-in-the-loop test results confirm the effectiveness of the proposed method.

Fault-tolerant design method for circuit system based on moment-independent importance

Fault-tolerant design method for circuit system based on moment-independent importance

Sequencing Optimization in k-out-of-n Cold-Standby Systems Considering Mission Cost

The k-out-of-n: G heterogeneous cold-standby system structure is a widely used fault-tolerant system design method, where the sequence in which the different system elements are initiated can greatly affect the system reliability and mission cost. This paper considers the optimal standby element sequencing problem (SESP) for such systems. Given the desired cold-standby redundancy level and fixed set of element choices, the objective of the optimal system design is to select the initiation sequence of the system elements so as to minimize the expected system mission cost while meeting a certain level of system reliability constraint. Based on a discrete approximation of time-to-failure distributions of the system elements, the system reliability and expected mission cost are evaluated simultaneously using a numerical method. A genetic algorithm is used as an optimization tool for solving the formulated SESP problem for k-out-of-n: G heterogeneous cold-standby systems. Examples are given to illustrate the considered problem and the proposed solution methodology.

Damage Tolerant Active Control: Concept and State of Art

Damage tolerant active control is a new research area related to fault tolerant control design methods applied to mechanical structures. It encompasses several techniques commonly used to design active vibration controllers and to detect and diagnose faults, as well to monitor structural integrity. Brief reviews of the common intersections of these areas are presented, with the purpose to clarify their interrelations and also to justify the new controller design paradigm. Some examples help to better understand the role of the new area.

Novel hazard-free majority voter for N -modular redundancy-based fault tolerance in asynchronous circuits

N -modular redundancy (NMR) is the simplest and most effective fault-tolerant design method for integrated circuits, where N copies of a circuit are employed and a majority voter produces the voted output. Asynchronous circuits, however, exhibit various characteristics that limit the applicability of NMR. Specifically, the hazard-free property of the output in these circuits must be preserved when hardware providing fault tolerance, such as a majority voter, is added. In this work, we first demonstrate that a typical majority voter design would fail to preserve the hazard-free property of its response. We then propose a hazard-free majority voter design for the triple-modular redundancy fault-tolerance design paradigm, which enters an output-holding state to preserve the output value when transient errors may be sensitised to its inputs. By exploring various conditions to exit from the output-holding state, we describe several extensions of the voter into an NMR one, each yielding a distinct implementation with different tolerance characteristics and area cost. We generalise this extension based on the exit condition and analyse the associated tolerance capability of the extended NMR voter. Finally, the proposed hazard-free voter is simulated using HSPICE, and detailed area cost formulations are derived for the proposed voter designs.

Fault-Tolerant Design and Testing of USB2.0 Peripheral Devices IP Core System

Universal serial bus 2.0 (USB2.0) is a kind of mainstream interface technology. The traditional USB developing is only to develop USB peripheral devices. For the USB2.0 peripheral devices IP core system that has wide application foreground, some interference inevitably exists in signal transmitting. Some fault-tolerant design and test methods must be adopted in order to correctly transmit and receive data. Combining with a project, this paper introduces in detail about measures, hardware implement, and test methods of fault-tolerant design about USB2.0 peripheral devices IP core system. Fault-tolerant design measures, noise reduction measures of signal processing, fault-tolerant methods about data encode and decode, package identification (ID) field fault-tolerant methods, and cyclic redundancy checks fault-tolerant methods are discussed. The paper also presents some hardware implement methods about fault-tolerant design of data decode and test methods about fault-tolerant design of USB2.0 IP core system. These methods can offer the reference for development of USB2.0 system in all kinds of electronics instrumentations.

Systematic fault simulation in an analog circuit simulator

With the recent increase in both fault isolation and fault tolerant design, automated and systematic methods of analyzing fault situations and their impact on the operation of solid-state circuitry are becoming increasingly important. In this paper we will explore the philosophy and techniques behind the design of a system for simulating various catastrophic failures in integrated circuits which is being implemented in a commercially available nodal circuit simulator ISPICE. We address the issues of how certain failure conditions can be identified and simulated, how certain sets of such conditions can be identified and used to reduce the cost of such a simulation without impacting the results, and how well structured reports can reduce large volumes of data to easily interpreted results. Finally, we also explore some of the more elaborate analysis and reporting techniques we expect to include in future implementations of automated fault diagnosis software.

Modeling of a Bubble-Memory Organization with Self-Checking Translators to Achieve High Reliability

This paper reports a study on the design and modeling of a highly reliable bubble-memory system. This system has the capability of correcting a single 16-adjacent bit-group error resulting from failures in a single basic storage module (BSM), and detecting with a probability greater than 0.99 any double errors resulting from failures in BSM's. The encoding/decoding network (memory translator) is designed to be self-checking, i.e., a single circuit failure in the translator wiH not produce an erroneous output that goes undetected. The system is able to perform reliable configuration in the event of uncorrectable BSM failures, memory translator failures, and dual-memory buffer failures; even in the presence of a single failure in the status registers controlling the configuration network. The bubble memory under study permits serial accessing of the store with 64 x 1024 bit blocks at a 100-kHz rate. The objective of this study is to develop good fault-tolerant design and analysis methods adequate for newly emerging technologies and prove the practicality by example. The reliability modeling study justifies the design philosophy adopted of employing memory data encoding and a translator to correct single group errors and detect double group errors to enhance the overall system reliability. By a proper design of the memory translator based on a new checking technique, a uniformly high percentage of multiple b-adjacent bit-group error detection is achieved through the use of a proposed code (detects 99.99695 percent of double b-adjacent bit-group errors and 99.9985 percent of triple or more b-adjacent bit-group errors).