Fault Injection Research Articles

Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference

AbstractNeural networks are widely used in critical environments such as healthcare, autonomous vehicles, or video surveillance. To ensure the safety of the systems that rely on their functionality, it is essential to validate their correct behaviour in the presence of faults. This paper studies the behaviour of state-of-the-art neural network models with fault injection in their weights. For this purpose, we analyse the sensitivity of these models and identify the impact of bit flips on their accuracy. To mitigate the effects of faults, we introduce two mechanisms that leverage bit-level redundancy for protection. The first mechanism, Fixed Protection, safeguards consecutive sets of bits, while the second, Variable Protection, targets non-consecutive bits. Our findings demonstrate that, on average, random bit flip faults cause the accuracy of the original models to drop by 1.3% to over 3%. However, with our protection mechanisms in place, accuracy reductions are significantly minimised, ranging from only 0.0001% to 0.4%.

Mixed skew cyclic codes over rings

This paper explores different types of skew cyclic codes by generating special subclasses with additional desirable properties. Specifically, we are interested in skew cyclic codes over mixed rings. We study some algebraic and structural properties of these codes and their constructions. We study skew cyclic codes over the mixed alphabet ring $\mathbb{F}_q(\mathbb{F}_q+v\mathbb{F}_q)$ under a mixed automorphism $(\theta,\tilde{\theta})$ and we give the structure of these codes for an arbitrary length via the non-commutative ring $\mathbb{F}_q[x,\theta](\mathbb{F}_q+v\mathbb{F}_q)[x,\tilde{\theta}]$. A condition for the existence of linear complementary dual (LCD) codes (which play an important role in practical applications such as armoring implementations against side-channel attacks and fault injection attacks) are explored specifically for skew cyclic codes.

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

Measurement of SET pulse width modulation in CMOS combinational logic by laser-induced fault injection

Watch Out for the Inherent Vulnerabilities in Developing Multi-tenant Cloud-FPGA: Communication Protocols

As FPGAs are being deployed in the cloud infrastructure for acceleration, the technology of multi-tenant FPGA has emerged as a topic of interest. This development has drawn considerable attention to its security issues. While previous research primarily focused on the security of applications, there has been limited exploration of the vulnerabilities inherent in FPGA IPs. In our work, we examine the vulnerabilities of two widely used data transmission protocols in modern FPGAs: the Advanced eXtensible Interface (AXI) and Peripheral Component Interconnect Express (PCIe). Our experiments, conducted with commercial FPGA development kits, launched fault injection attacks through the shared power distribution network (PDN). Through non-invasive electromagnetic (EM) trace measurement, we characterize the voltage fluctuation across various attack patterns. Subsequently, we simulate real-world data transfers using two crafted datasets with different statistical characteristics. The experimental results demonstrate the unique security vulnerabilities of the current AXI and PCIe protocols in the context of a multi-tenant cloud-FPGA. In response to such vulnerability, we further propose two defense strategies: InChAXI that utilizes integrity checking for AXI-based data, and FCPCIe that employs frequency scaling for PCIe-based data. The performance evaluation demonstrates that our proposed defenses can significantly reduce the fault injections on the AXI-based data transmission by 705 times with small overheads – 0.5% in hardware footprint and 7.9% in latency, respectively. On the other hand, FCPCIe effectively prevents the fault injection attack during the PCIe-based data transmission by reducing the user clock frequency, while incurring a 10.13% overhead on data throughput.

Research on Electric Vehicle Powertrain Systems Based on Digital Twin Technology

As a critical component of electric vehicles, the powertrain has a significant impact on the overall performance of vehicles. In addressing the challenge of lengthy testing cycles, this study develops a para model of the powertrain, utilizing digital twin (DT) technology, thereby establishing a framework for simulation testing of multi-controller intermodulation. We establish functional definition coverage testing by designing specific functional requirement use cases, and we validate the failure mechanism via fault injection use cases. The results indicate that the DT testing platform can effectively simulate the operational interactions among various controllers within the powertrain system. In comparison to traditional field testing, the digital twin-based testing methodology offers enhanced operational efficiency and allows for the examination of testing conditions that are impractical to implement in real vehicles, particularly in the context of fault injection testing, thus facilitating the early detection of potential safety risks within the system. The advancement of this technical solution holds significant practical implications for the future mass production and development of electric vehicles.

AttackDefense Framework (ADF): Enhancing IoT Devices and Lifecycles Threat Modeling

Threat modeling (TM) is essential to manage, prevent, and fix security and privacy issues in our society. TM requires a data model to represent threats and tools to exploit such data. Current TM data models and tools have significant limitations preventing their usage in real-world scenarios. For example, it is challenging to TM embedded devices with current data models and tools as they cannot model their hardware, firmware, and low-level software. Moreover, it is impossible to TM a device lifecycle or security-privacy tradeoffs as these data models and tools were developed for other use cases (e.g., software security or user privacy). We fill this relevant gap by presenting the AttackDefense Framework (ADF), which provides a novel data model and related tools to augment TM. ADF’s building block is the AD object that can be used to represent heterogeneous and complex threats. Moreover, ADF provides automations to process a collection of AD objects, including ways to create sets, maps, chains, trees, and wordclouds of AD objects. We present ADF , a toolkit implementing ADF composed of four modules (Catalog, Parse, Check, and Analyze). We confirm that the data model and tools provided by ADF are useful by running an extensive set of experiments while threat modeling a crypto wallet and its lifecycle. Our experiments involved seven expert groups from academia and industry, each using the ADF on an orthogonal threat class. The evaluation generated 175 high-quality ADs covering ISA/IEC 62433-4-1 SecDev Lifecycle, side-channels, fault injection, microarchitectural attacks, speculative execution, pre-silicon testing, invasive physical chip modifications, Bluetooth protocol and implementation threats, and FIDO2 authentication.

Hardware Security Breaches: Alarming Exploits Beyond Tampering

Side Channel Attacks (SCAs) and Fault Injection Attacks have emerged as significant threats to the security of electronic devices. This paper explores these hardware attack vectors in the context of recent incidents [11] involving pagers and walkie-talkies. We shall deep dive into the possible mechanisms of these attacks, how they can be combined for increased efficacy, and their implications for device security. This paper discusses only the possible ways [1] the adversaries could have exploited and may include other attack vectors such as supply chain attack and few others. The aim of this paper as we discuss the potential attack mechanisms is only to focus on mitigations and awareness of the reader to perform advanced security testing.

Research on fault diagnosis for three-phase rectifier device in direct current transmission system based on continuous wavelet transform and vision transformer

Abstract As a core component of photovoltaic power generation systems, the three-phase rectifier device plays a crucial role, and its failure can potentially reduce energy conversion efficiency and output quality. Presently, the performance of fault time-domain signal diagnosis methods based on three-phase rectifier circuits is challenging to enhance. This paper proposes a novel fault detection method for three-phase rectifier devices based on Vision Transformer, referred to as CWT-ViT, to address this issue. This method transforms time-domain fault signals into images through Continuous Wavelet Transform (CWT), subsequently inputting these images into a Vision Transformer model. Relying on its powerful self-attention mechanism and fully connected layers, it realizes the extraction and learning of rectifier device image features. A Simulink simulation model of a three-phase bridge controllable rectifier circuit is established for fault injection to collect fault signals. Fault diagnosis experiments demonstrate that the proposed diagnostic method achieves a prediction accuracy of 98.6%, maintaining a relatively high precision level. In comparison to four excellent classification models currently available: AlexNet, RepVGG, ResNet, and GoogLeNet, the proposed method demonstrates superior diagnostic performance. Additionally, this paper conducts ablation experiments to meticulously analyze the impact of each module in the fault diagnosis process. This research achieves more precise and efficient fault diagnosis in photovoltaic power generation systems, thereby reducing downtime and maintenance costs for actual equipment and enhancing the stability of photovoltaic power generation systems. This research provides an innovative, intelligent solution for the intelligent operations and maintenance of photovoltaic power generation.

BUFIT: FINE-GRAINED DYNAMIC BURST FAULT INJECTION TOOL FOR EMBEDDED field programmable gate array TESTING

Fault injection (FI) is a well-known method to attack embedded systems, particularly advanced FPGAs and microcontrollers physically. The FPGA-based embedded system constitutes SRAM for configuration data storage. Multiple-bit upset is a main threat for FPGAs due to technology scaling and complex application bit files. Space environments additionally incur radiation threats to these devices. This paper proposes burst error modeling and a burst fault injection tool (BUFIT) to address these issues. BUFIT has been proposed with fine-grained and coarse-grained circuits. Built-in instrumented FPGA-based FI is proposed for effectively injecting MBUs in configuration memory with space adaptive rate for accurately estimating soft errors. Evaluation of proposed BUFIT on Kintex-7 target FPGA to various OR 1200-based workloads is given to analyze the speed up of the proposed technique. Results on the OR 1200 processor show that BUFIT is three and two orders of magnitude faster than existing DPR and SCFIT techniques. It uses only 0.4 % CLB overhead and has negligible impact on FFs of target SFPGAs.

Model and Method for Providing Resilience to Resource-Constrained AI-System.

Artificial intelligence technologies are becoming increasingly prevalent in resource-constrained, safety-critical embedded systems. Numerous methods exist to enhance the resilience of AI systems against disruptive influences. However, when resources are limited, ensuring cost-effective resilience becomes crucial. A promising approach for reducing the resource consumption of AI systems during test-time involves applying the concepts and methods of dynamic neural networks. Nevertheless, the resilience of dynamic neural networks against various disturbances remains underexplored. This paper proposes a model architecture and training method that integrate dynamic neural networks with a focus on resilience. Compared to conventional training methods, the proposed approach yields a 24% increase in the resilience of convolutional networks and a 19.7% increase in the resilience of visual transformers under fault injections. Additionally, it results in a 16.9% increase in the resilience of convolutional network ResNet-110 and a 21.6% increase in the resilience of visual transformer DeiT-S under adversarial attacks, while saving more than 30% of computational resources. Meta-training the neural network model improves resilience to task changes by an average of 22%, while achieving the same level of resource savings.

SAT-based Formal Verification of Fault Injection Countermeasures for Cryptographic Circuits

Fault injection attacks represent a type of active, physical attack against cryptographic circuits. Various countermeasures have been proposed to thwart such attacks, however, the design and implementation of which are intricate, error-prone, and laborious. The current formal fault-resistance verification approaches are limited in efficiency and scalability. In this paper, we formalize the fault-resistance verification problem and show that it is coNP-complete. We then devise a novel approach for encoding the fault-resistance verification problem as the Boolean satisfiability (SAT) problem so that modern off-the-shelf SAT solvers can be utilized. The approach is implemented in an open-source tool FIRMER which is evaluated extensively on realistic cryptographic circuit benchmarks. The experimental results show that FIRMER is able to verify fault-resistance of almost all (72/76) benchmarks in 3 minutes (the other three are verified in 35 minutes and the hardest one is verified in 4 hours). In contrast, the prior approach fails on 31 fault-resistance verification tasks even after 24 hours (per task).

Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults

Fault injection attacks are a serious threat to system security, enabling attackers to bypass protection mechanisms or access sensitive information. To evaluate the robustness of CPU-based systems against these attacks, it is essential to analyze the consequences of the fault propagation resulting from the complex interplay between the software and the processor. However, current formal methodologies combining hardware and software face scalability issues due to the monolithic approach used. To address this challenge, this work formalizes the k-fault-resistant partitioning notion to solve the fault propagation problem when assessing redundancy-based hardware countermeasures in a first step. Proven security guarantees can then reduce the remaining hardware attack surface when introducing the software in a second step. First, we validate our approach against previous work by reproducing known results on cryptographic circuits. In particular, we outperform state-of-the-art tools for evaluating AES under a three-fault-injection attack. Then, we apply our methodology to the OpenTitan secure element and formally prove the security of its CPU’s hardware countermeasure to single bit-flip injections. Besides that, we demonstrate that previously intractable problems, such as analyzing the robustness of OpenTitan running a secure boot process, can now be solved by a co-verification methodology that leverages a k-fault-resistant partitioning. We also report a potential exploitation of the register file vulnerability in two other software use cases. Finally, we provide a security fix for the register file, prove its robustness, and integrate it into the OpenTitan project.

MicroFI: Non-Intrusive and Prioritized Request-Level Fault Injection for Microservice Applications

MicroFI: Non-Intrusive and Prioritized Request-Level Fault Injection for Microservice Applications

Evaluating single event upsets in deep neural networks for semantic segmentation: An embedded system perspective

As the deployment of artificial intelligence (AI) algorithms at edge devices becomes increasingly prevalent, enhancing the robustness and reliability of autonomous AI-based perception and decision systems is becoming as relevant as precision and performance, especially in applications areas considered safety-critical such as autonomous driving and aerospace. This paper delves into the robustness assessment in embedded Deep Neural Networks (DNNs), particularly focusing on the impact of parameter perturbations produced by single event upsets (SEUs) on convolutional neural networks (CNN) for image semantic segmentation. By scrutinizing the layer-by-layer and bit-by-bit sensitivity of various encoder–decoder models to soft errors, this study thoroughly investigates the vulnerability of segmentation DNNs to SEUs and evaluates the consequences of techniques like model pruning and parameter quantization on the robustness of compressed models aimed at embedded implementations. The findings offer valuable insights into the mechanisms underlying SEU-induced failures that allow for evaluating the robustness of DNNs once trained in advance. Moreover, based on the collected data, we propose a set of practical lightweight error mitigation techniques with no memory or computational cost suitable for resource-constrained deployments. The code used to perform the fault injection (FI) campaign is available at https://github.com/jonGuti13/TensorFI2, while the code to implement proposed techniques is available at https://github.com/jonGuti13/parameterProtection.

Fault-tolerant deep learning inference on CPU-GPU integrated edge devices with TEEs

CPU-GPU integrated edge devices and deep learning algorithms have received significant progress in recent years, leading to increasingly widespread application of edge intelligence. However, deep learning inference on these edge devices is vulnerable to Fault Injection Attacks (FIAs) that can modify device memory or execute instructions with errors. We propose DarkneTF, a Fault-Tolerant (FT) deep learning inference framework for CPU-GPU integrated edge devices, to ensure the correctness of model inference results by detecting the threat of FIAs. DarkneTF introduces algorithm-based verification to implement the FT deep learning inference. The verification process involves verifying the integrity of model weights and validating the correctness of time-intensive calculations, such as convolutions. We improve the Freivalds algorithm to enhance the ability to detect tiny perturbations by strengthening randomization. As the verification process is also susceptible to FIAs, DarkneTF offloads the verification process into Trusted Execution Environments (TEEs). This scheme ensures the verification process’s security and allows for accelerated model inference using the integrated GPUs. Experimental results show that GPU-accelerated FT inference on HiKey 960 achieves notable speedups ranging from 3.46x to 5.57x compared to FT inference on a standalone CPU. The extra memory overhead incurred FT inference remains at an exceedingly low level, with a range of 0.46% to 10.22%. The round-off error of the improved Freivalds algorithm is below 2.50×10−4, and the accuracy of detecting FIAs is above 92.73%.

Virtualized Fault Injection Framework for ISO 26262-Compliant Digital Component Hardware Faults

Simulation-based Fault Injection (FI) is crucial for validating system behaviour in safety-critical applications, such as the automotive industry. The ISO 26262 standard’s Part 11 extension provides failure modes for digital components, driving the development of new fault models to assess software-implemented mechanisms against random hardware failures (RHF). This paper proposes a Fault Injection framework, QEFIRA, and shows its ability to achieve the failure modes proposed by Part 11 of the ISO 26262 standard and estimate relevant metrics for safety mechanisms. QEFIRA uses QEMU to inject permanent and transient faults during runtime, whilst logging the system state and providing automatic post-execution analysis. Complemented with a confusion matrix, it allows us to gather standard compliant metrics to characterise and evaluate different designs in the early stages of development. Comparatively to the native QEMU implementation, the tool only shows a slowdown of 1.4× for real-time microcontroller-based applications.

When Amnesia Strikes: Understanding and Reproducing Data Loss Bugs with Fault Injection

We present LazyFS, a new fault injection tool that simplifies the debugging and reproduction of complex data durability bugs experienced by databases, key-value stores, and other data-centric systems in crashes. Our tool simulates persistence properties of POSIX file systems (e.g., operations ordering and atomicity) and enables users to inject lost and torn write faults with a precise and controlled approach. Further, it provides profiling information about the system's operations flow and persisted data, enabling users to better understand the root cause of errors. We use LazyFS to study seven important systems: PostgreSQL, etcd, Zookeeper, Redis, LevelDB, PebblesDB, and Lightning Network. Our fault injection campaign shows that LazyFS automates and facilitates the reproduction of five known bug reports containing manual and complex reproducibility steps. Further, it aids in understanding and reproducing seven ambiguous bugs reported by users. Finally, LazyFS is used to find eight new bugs, which lead to data loss, corruption, and unavailability.

Testing Error Handling Code With Software Fault Injection and Error-Coverage-Guided Fuzzing

Real-world programs require error handling code to handle various kinds of possible errors. However, these errors just infrequently occur due to special conditions, so error handling code is difficult to test. Coverage-guided fuzzing and software fault injection (SFI) are two common techniques that can test error handling code, but they still have major limitations. Specifically, existing fuzzing approaches generate program inputs guided by code coverage, but many occasional errors (such as insufficient memory) are unrelated to inputs, and code coverage cannot effectively reflect the execution contexts of these errors; existing SFI approaches often inject single or random faults, without exploring fault space or using program feedback. In this paper, we propose a new fuzzing framework named EH-Fuzz, to effectively test error handling code. EH-Fuzz uses a context-sensitive SFI-based fuzzing approach to explore fault space and perform fault injection, guided by a new metric named <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">error coverage</i> . We evaluate EH-Fuzz on 9 user-level programs and 6 kernel-level modules, and find 45 new real bugs, 31 of which have been confirmed and fixed. We compare EH-Fuzz to existing fuzzing approaches (including AFL, AFL++, Syzkaller, FIZZER and FIFUZZ), and EH-Fuzz finds many real bugs missed by these approaches with higher testing coverage.

Finding Fault Injection Location via Evaluation of Electromagnetic Emission from Cryptographic ICs

Finding Fault Injection Location via Evaluation of Electromagnetic Emission from Cryptographic ICs

Avionics Module Fault Diagnosis Algorithm Based on Hybrid Attention Adaptive Multi-Scale Temporal Convolution Network.

Since the reliability of the avionics module is crucial for aircraft safety, the fault diagnosis and health management of this module are particularly significant. While deep learning-based prognostics and health management (PHM) methods exhibit highly accurate fault diagnosis, they have disadvantages such as inefficient data feature extraction and insufficient generalization capability, as well as a lack of avionics module fault data. Consequently, this study first employs fault injection to simulate various fault types of the avionics module and performs data enhancement to construct the P2020 communications processor fault dataset. Subsequently, a multichannel fault diagnosis method, the Hybrid Attention Adaptive Multi-scale Temporal Convolution Network (HAAMTCN) for the integrated functional circuit module of the avionics module, is proposed, which adaptively constructs the optimal size of the convolutional kernel to efficiently extract features of avionics module fault signals with large information entropy. Further, the combined use of the Interaction Channel Attention (ICA) module and the Hierarchical Block Temporal Attention (HBTA) module results in the HAAMTCN to pay more attention to the critical information in the channel dimension and time step dimension. The experimental results show that the HAAMTCN achieves an accuracy of 99.64% in the avionics module fault classification task which proves our method achieves better performance in comparison with existing methods.