Fault-free Cells Research Articles

Loop-based design and reconfiguration of wafer-scale linear arrays with high harvest rates

Design and reconfiguration approaches for high harvest rates and parallel on-wafer diagnosis of linear arrays are described. The defect-tolerant designs use multiplexers to switch intercell connections and guarantee that the wire length between any two logically adjacent cells is constant, independent of fault distribution. The designs are appropriate for implementing linear arrays of wafer-scale memory and processor architectures. The harvesting of fault-free cells into a linear array is a percolation process; there exists a critical cell yield such that the harvest rate drops to zero (approaches 100%) if the cell yield is below (above) the critical value. Finding a maximum-size linear array for a given set of fault-free cells is polynomial time solvable if only the interconnections between fault-free cells are utilized, but is NP-complete if the interconnections between all cells are utilized. A heuristic reconfiguration algorithm utilizing the interconnections between all cells is presented. Application of boundary scan to parallel testing and on-wafer diagnosis of the arrays is described. >

Design of self-testable wafer-scale processor arrays

A technique for designing self-testable wafer-scale arrays is presented. Faulty and Fault-free cells (processors, PEs) are indentified in distributed fashion without providing correct responses from the outside. It uses both local comparisons and dissemination of the comparison results. Faults in diagnostic circuits, which have been typically assumed to be fault-free, are also covered by the self-testing algorithm. The algorithm is quite general in the sense that it is independent of the structure of the syndrome analyser in each cell.

Reconfiguration of VLSI arrays by covering

In VLSI arrays, redundant cells are added as spares. The proposed approach is applicable as an offline technique at either production time and/or run time. Reconfiguration is implemented by index mapping using a sequence of two operators. A reconfiguration algorithm which utilizes index mapping is proposed. This algorithm uses a new approach to the assignment problem. It is shown that reconfiguration of fault-free cells is equivalent to a covering of faulty cells by spare cells. It is also established that in a two-dimensional array the optimal spare assignment is given by a maximum matching. This translates to a maximum flow. It is shown that a variation of the matching preserves the optimality of the assignment, while reducing the time complexity of the reconfiguration algorithm Characterization theorems for index mapping and simulation results to substantiate the practicality of the approach are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>