Fault Emulation Research Articles

Synchronous Generator Stability Characterization for Gas Power Plants Using Load Rejection Tests

For power grid operators, knowing the transient response of the synchronous generators (SGs) included in their grids is important in order to simulate and monitor faults and other contingencies. However, the time constant of the automatic voltage regulator (AVR) and speed governors of SGs are not fast enough to show their transient dynamics in the case of a fault in the grid. This paper presents a fieldwork carried out in more than 60 gas power plants, where the response of their controllers was studied. These power plants are running and supplying electricity to the Spanish grid. The study consists of recording some SG responses in different situations, varying the AVR or the speed governor setpoints while the generator is running at no-load conditions, and also performing load rejection tests, achieving a real fault emulation. Once all the data are gathered, a fitting of the SG parameters is performed by computer simulations using GENSAL, GAST and SEXS models replicating the performed field tests. This work allows us to build an accurate network model for the whole power system and check which plants are having trouble in the case of contingencies in the grid.

Island detection for grid connected photovoltaic distributed generations via integrated signal processing and machine learning approach

The applications of distributed generators in distribution networks have proven to be highly reliable and cost-effective. Accidental islanding is currently regarded as an undesirable operational mode in utility practice because it can harm individuals and connected systems. Therefore, the occurrence of islanding must be detected, and then distributed generators must be disconnected from the main network. In this article, a fast and accurate island detection method is proposed for photovoltaic distributed generations with a near-zero non-detection zone. A new island detection approach is developed by combining signal processing and machine learning techniques. Variational mode decomposition is used as a signal processing technique. Whereas the ensemble bagged-trees method is used as a machine learning technique. Variational mode decomposition is used to process positive- and negative-sequence component voltage signals along with power signal measurements acquired from the point of common coupling in order to identify intrinsic-mode functions. Next, the ensemble bagged-trees method is utilized to detect islanding during active and reactive power mismatch events and inconvenient quality factors. The results demonstrate that the suggested technique is able to discriminate between islanding and non-islanding events such as capacitive switching, fault emulation, and distribution generation cut-off. Besides, it has a minimum non-detection zone of less than 4% and a 4.8 ms detection time. Therefore, it is a reliable and reasonable solution for the distribution grid.

Induction Machine Emulation for Variable Frequency Drive Converter Faults

Voltage in current out (VICO) models are commonly used for induction machine (IM) emulation. This model does not provide the information of back-emf and hence cannot be used for open circuit fault emulation. A current in voltage out model (CIVO) is an alternate IM model where it provides back-emf information. However, the CIVO model cannot be used directly with the conventional emulator configuration. Hence, in this paper, a new emulator configuration has been proposed to accommodate the CIVO model. The model is used in a new emulator configuration by incorporating physical emulator parameters. The paper further discusses the upgrade of the model considering saturation nonlinearities. The emulator employing such a model mimics the real induction machine back-emf with high accuracy. The proposed emulator is tested for different gate driver faults such as single switch and multiple switch open faults, starting and speed changing conditions. The experimental results are validated with a 5 hp machine. Different fault signatures are also identified with the help of the emulator to help with fault diagnosis and localization.

Evaluation of fault injection tools for reliability estimation of microprocessor-based embedded systems

Statistical fault injection is widely used to estimate the reliability of mission-critical microprocessor-based systems when exposed to radiation and to evaluate the performance of fault mitigation strategies. However, further research is needed to gain a better understanding of the accuracy of the results and the feasibility of their application under realistic radiation conditions. In this article, an understanding of scenarios in which Instruction Set Architecture simulators or emulators may be relied upon for realistic statistical fault injection campaigns is advanced. An analysis is presented of the results from two simulation-based fault injection tools versus a set of fault emulation results on a real processor. The conclusions of the analysis assist the selection of the most efficient tool and method for testing many different software-based fault mitigation techniques within reasonable time periods and at affordable costs throughout an irradiation campaign. In particular, it was established that a partially ordered set of relations could be defined on the basis of statistical fault injection in relation to the effects of different versions of an application and a given simulator that remained unaltered during the irradiation experiments. The tests were conducted with a Texas Instruments MSP430 microcontroller to perform both fault injection campaigns and irradiation experiments using neutrons at the Los Alamos Neutron Science Center (LANSCE) Weapons Neutron Research Facility at Los Alamos, USA.

ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs

Fault emulation in field-programmable gate arrays (FPGAs) is a popular alternative to test the reliability of a design due to its low cost and high availability compared to traditional radiation-based approaches. Fault emulation is an instrumentation method based on inducing artificial bit flips on the design under test (DUT) to modify the content of its memory elements or the structure of the design itself. A major limitation of error emulation in FPGAs lies in the determination of the proper bits to test, which is directly related to the reliability results obtained and the execution times of the fault injection campaign. The Automatic Configuration Memory Error-injection (ACME) tool helps with this process in Xilinx FPGAs by obtaining the essential bits of an FPGA region where the DUT is. In this paper, we present ACME-2, an improved version of the tool where the translation from the FPGA region to design essential bits has been modified with architectural information of the FPGA. In this revision of the tool, redundant input/output routing bits that distort the reliability results are minimized. For the example designs used in the experiments, these modifications have led to an improvement in the precision of the reliability results as well as a reduction of the fault injection campaign runtime over the previous version of the tool.

Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor

The RISC-V instruction set architecture open licensing policy has spawned a hive of development activity, making a range of implementations publicly available. The environments in which RISC-V operates have expanded correspondingly, driving the need for a generalized approach to evaluating the reliability of RISC-V implementations under adverse operating conditions or after normal wear-out periods. Fault injection (FI) refers to the process of changing the state of registers or wires, either permanently or momentarily, and then observing execution behavior. The analysis provides insight into the development of countermeasures that protect against the leakage or corruption of sensitive information, which might occur because of unexpected execution behavior. In this article, we develop a hardware–software co-design architecture that enables fast, configurable fault emulation and utilize it for information leakage and data corruption analysis. Modern system-on-chip FPGAs enable building an evaluation platform, where control elements run on a processor(s) (PS) simultaneously with the target design running in the programmable logic (PL). Software components of the FI system introduce faults and report execution behavior. A pair of RISC-V FI-instrumented implementations are created and configured to execute the Advanced Encryption Standard and Twister algorithms. Key and plaintext information leakage and degraded pseudorandom sequences are both observed in the output for a subset of the emulated faults.

A fault diagnostic approach based on PSO-HMM for underwater thrusters.

In this paper, we describe an approach based on improved Hidden Markov Model (HMM) for fault diagnosis of underwater thrusters in complex marine environments. First, considering the characteristics of thruster data, we design a three-step data preprocessing method. Then, we propose a fault classification method based on HMMs trained by Particle Swarm Optimization (PSO) for better performance than methods based on vanilla HMMs. Lastly, we verify the effectiveness of the proposed approach using thruster samples collected from a fault emulation experimental platform. The experiments show that the PSO-based training method for HMM improves the accuracy of thruster fault diagnosis by 17.5% compared with vanilla HMMs, proving the effectiveness of the method.

Adaptive sensorless PMSM mechanical fault detection with varying speeds

In this paper, we propose to improve an OSG (Orthogonal Signal Generator) based technique in order to extract mechanical faults from a PMSM (Permanent Magnet Synchronous Motor) with variable mechanical speed. This technique is part of the MCSA (Motor Current Signal Analysis) family. In this particular case, we use a single current measurement. The technique can be used on-line and without a mechanical speed sensor. A stability analysis of the adaptive OSG method is presented in this paper. Order tracking extraction is added to ensure robust analysis and detection of variable speed faults. A comparison is made with the Concordia and TKEO (Teager Kaiser Enregy Operator) methods on an experimental bench with a mechanical fault emulator. A statistical study of the fault detection is conducted based on the experimental results

Extensive fault emulation on RFID tags for fault tolerance and security evaluation

Radio frequency identification (RFID) is widespread and still necessary in many important applications. However, and in various significant cases, the use of this technology faces multiple security issues that must be addressed. This is mainly related to the use of RFID tags (transponders) which are electronic components communicating wirelessly, and hence they are vulnerable to multiple attacks through several means. Thus, it is challenging to evaluate the hardness of such devices. To tackle this problem, an extensive fault analysis is performed on an ultra-high frequency (UHF) tag architecture. Tens of millions of single-bit upsets (SBUs) and multiple-bit upsets (MBUs) faults have been emulated randomly on this tag architecture using an FPGA (field programmable gate arrays)-based emulation platform. The emulated faults have been classified into five groups according to faults effect on the tag behavior. Then, we propose a classification of emulated fault in function of MBU size and an error analysis with the aim of distinguishing between major and minor errors. Thus, experimentation results allowed a thorough evaluation of the tag robustness against MBUs. The proposed approach stands for an efficient means for studying tag architectures at the design level and evaluating their robustness and vulnerability to fault attacks and disturbances of harsh environments.

DOMREP–An Orthogonal Countermeasure for Arbitrary Order Side-Channel and Fault Attack Protection

Protection against physical attacks is a major requirement for cryptographic implementations on devices which can be accessed by attackers. Side-channel and fault injection attacks are the most common types of physical attacks. In this work we present a novel generic solution for simultaneous protection against side-channel and fault attacks with arbitrary order. We combine domain oriented masking and repetition codes in an orthogonal way and call this approach DOMREP. The resistance against side-channel attacks and fault attacks can be scaled independently of each other, for the protection against higher-order side-channel analysis and the injection of multiple faults including SIFA. We develop the generic concept of orthogonal protection, and implement the DOMREP concept on GIMLI, a round two NIST LWC competition candidate, on a Xilinx Artix-7 FPGA. Our implementation of GIMLI is verified to be resistant against univariate first-order side-channel attacks by TVLA. The resistance against SIFA is verified by means of fault emulation of single as well as multiple bit faults. Our implementation of GIMLI achieves the expected security level according to these measurements. We also provide numbers for the area overhead for our protected implementation of GIMLI.

Identification and Classification of Stator Inter-Turn Faults in Induction Motor Using Wavelet Kernel Based Convolutional Neural Network

This paper presents an efficient technique for early diagnosis of simultaneous faults in different phases of stator winding of a three-phase induction motor due to turn-to-turn short circuit. A real-life motor has been designed and manufactured with fault emulation features in all the phases of stator winding. Phase currents are recorded by a data acquisition system for different fault conditions. Wavelet kernel-based convolutional neural network (WK-CNN) has been employed for identification and classification of the faults using the recorded current signatures. Various mother wavelets have been tested as convolution filters to extract salient features from the recorded current signatures followed by updating the weights of the filter at each epoch by a supervised learning algorithm. The reason to use a deep framework based on CNN is that it eliminates the requirement of feature extraction and classification algorithms separately. The proposed method also shows promising results when signals are contaminated by the noises, which is always a challenge in an industrial environment. Comparative results show the effectiveness of the proposed technique over the state-of-the-art methods.

Assessment of a Hardware-Implemented Machine Learning Technique Under Neutron Irradiation

Hardware-implemented intelligent systems running autonomous functions and decisions are today becoming more and more ubiquitous in many fields of applications, demanding reliable operation even under harsh conditions as in nuclear power plants and avionics altitudes. Support vector machine (SVM) is a prominent machine learning solution to optimize hardware-implemented autonomous systems. This paper is the first to assess the operation of a field-programmable gate array (FPGA)-designed SVM architecture under radiation effects. A fault emulation campaign along with radiation test experiments with a 14-MeV neutron generator has been performed, and the results show that 27% of the neutron radiation-induced errors in the target SVM architecture provoked critical failures.

Development of a Converter-Based Transmission Line Emulator With Three-Phase Short-Circuit Fault Emulation Capability

A transmission line emulator has been developed to flexibly represent interconnected ac lines under normal operating conditions in a voltage-source-converter-based power system emulation platform. As the most serious short-circuit fault condition, the three-phase short-circuit fault emulation is essential for power system studies. This paper proposes a model to realize a three-phase short-circuit fault emulation at different locations along a single transmission line or one of several parallel-connected transmission lines. At the same time, a combination method is proposed to eliminate the undesired transients caused by the current reference step changes while switching between the fault state and the normal state. Experiment results verify the developed transmission line three-phase short-circuit fault emulation capability.

Emulating single point bearing faults with the use of an active magnetic bearing

The propagation of evolving mechanical faults in rotating electric machinery and their corresponding signatures in the machines’ electrical signals is still not elucidated thoroughly. This deficiency implies serious obstructions in the development of using those signals as a complete and reliable condition monitoring technology. This study presents a new method to translate single point outer and inner race bearing faults into specific movements of the rotor with respect to the stator. The method contains the excitation of a simplified mass-spring-damper bearing model by analytical constructed fault-related force functions. Furthermore, a novel approach in order to emulate those obtained specific fault-related rotor movements with the use an experimental test setup is described, dimensioned, simulated and validated. Replacing the drive-end bearing of the induction machine under test by an active magnetic bearing creates the opportunity to continuously manipulate the rotor's position. The estimated single point bearing fault-related rotor movements serve as set-point for the magnetic bearing, resulting in the achievement of a single point bearing fault emulator with high relevance and reproducibility. This study includes experimental results of an emulated single point outer race bearing fault on an 11 kW induction machine.

Fault diagnosis in switched‐linear systems by emulation of behavioral models on FPGA: A case study of current‐mode buck converter

AbstractThis paper presents an Field‐Programmable Gate Array (FPGA)‐based fault emulation and detection framework for switched‐linear systems commonly encountered in power electronics. The proposed framework exploits high‐level behavioral modeling that maps analog functionality into fixed‐point architectures supported by FPGAs. This work is mainly concerned with modeling and validation of effectiveness of a fault diagnoser of a power converter much before its fabrication. The proposed concept of fault diagnosis at presilicon stage overcomes several reliability issues in power electronic systems and enables design and development of test resources, verification of test bed, and interconnecting circuitry at an early stage of the design. To illustrate applicability of this environment, well‐accepted fault events including hard and soft faults are emulated with the help of a nonideal model of a buck converter and a piecewise linear detection filter, which follow an observer‐based residual generation for fault detection. The paper also shows that the proposed method is equally applicable for detection of faults under unstable operation of the converter. The effectiveness of the proposed framework is evaluated through FPGA‐based simulation (or “emulation”) of a peak‐current‐mode–controlled buck‐type switching converter implemented on Xilinx Kintex‐7 FPGA in MATLAB/Simulink environment with Xilinx System Generator support. To the best of our knowledge, fault diagnosis in power converter by emulation of its nonideal model on FPGA is attempted for the first time in the literature. Experimental results show that power converter faults can be easily detected by monitoring detection filter residuals while some of the faults can be precisely identified.

An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs

FPGA-based emulation of permanent faults in ASICs can considerably improve the fault simulation time compared to traditional software-based approaches. Moreover, a hardware-based solution provides realistic behavior during fault emulation which is often required in safety-critical systems' validation. Previous emulation approaches not only suffers from considerable area (for instrumentation) and reconfiguration (for fault injection) overheads but also provides limited coverage of the target faults (and fault sites). The latter is due to difficulties in establishing a fault model equivalence when the ASIC structural netlist is passed through the design automation phases of an FPGA. This paper presents a novel approach for fast emulation of permanent faults in ASICs on state-of-the-art dynamically reconfigurable SRAM-based FPGAs while achieving fault model equivalence. Our proposed approach leverages localized run-time in-place Look Up Table (LUT) reconfigurations to avoid the time-consuming bitstream generation process for every ASIC fault. Moreover, the speed of fault injection is enhanced by direct LUT configuration data modification inside a bitstream frame. This results in 17 and 4 times improvements in fault injection speeds over vendor-provided LUT modification libraries and existing partial bitstream based approaches respectively. However, this improvement is achieved at an average 1.2 and 1.1 times degradation in area and delay metrics for the considered mapped circuits which is affordable considering the benefits in terms of the emulation speed.

Amplification of Single Mechanical Fault Signatures Using Full Adaptive PMSM Observer

This paper presents a localized mechanical fault detection method using a full adaptive permanent-magnet synchronous machine (PMSM) observer in a d / q reference frame. It appears that the fault sensitivity of PMSM stator currents and rotor speed measurements is very low with regard to single mechanical faults. That is why an amplification of single mechanical fault signatures in frequency domain is proposed by adjusting the adaptive PMSM observer gains. To study the influence of the adaptive PMSM observer gains on fault signatures, the observer model is first of all linearized at an operating point. Then, the static gain, the resonance, and the quality factor Q of different transfer functions are analyzed. A dedicated experimental setup based on an original mechanical fault emulator and a 7.8 kW PMSM drive is designed to validate the simulation results. The simulation and the experimental results show that the proposed method is effective to amplify single mechanical fault signatures and the calculated fault indicator.

Emulation-based fault analysis on RFID tags for robustness and security evaluation

This paper presents an FPGA (field-programmable gate array) based fault emulation system for analysis of fault impact on security and robustness of RFID (radio frequency identification) tags. This emulation system that deals with any RFID protocol consists of two tag-reader pairs, a fault injection module and an emulation controller all implemented in a single FPGA. The designed approach performs single event upset (SEU) and single event transient (SET) fault injection and permits with high flexibility to set communication scenarios and related parameters. Moreover, we propose a classification of produced errors to evaluate fault impacts and identify most sensitive tag flip-flops causing large number of failures and security concerns. The proposed fault injection approach provides suitable means to increase tags' security and robustness. In our experimentation campaign, an ultra-high frequency (UHF) tag architecture has been exposed to intensive SEU and SET fault injections. The duration of the campaign including results analysis is 30min in where 6,215,316 faults are experimented. Our results have shown that the tag has tolerated 61.82% of SEUs and 67.83% of SETs. The flip-flops that constitute the tag FSM (finite state machine) have been identified as the most sensitive parts causing large number of failures.

Towards an efficient SEU effects emulation on SRAM-based FPGAs

A novel fault injection approach, reproducing results obtained from radiation ground testing while studying the Single Event Upset (SEU) effects on SRAM-based Field Programmable Gate Arrays (FPGAs), is presented. This approach can take into account the relative sensitivity difference between configuration bits set to ‘0’ and those set to ‘1’. According to irradiation experiments conducted under proton beam for a Xilinx Virtex-5 FPGA at the TRIUMF lab, configuration bits set to ‘1’ are approximately twice as sensitive as bits set to ‘0’. This fact was exploited in test sequence generation while performing fault injection experiments, in order to generate more realistic emulation results. The effectiveness of the approach is validated by comparing its results to those obtained with proton radiation tests, for two different ring-oscillator-based experimental setups. It shows that taking this sensitivity into account helps obtain more realistic results while dealing with delays induced by radiation, which justifies considering this relative sensitivity during fault emulation. In fact, comparing the results obtained from the proposed approach to those obtained at TRIUMF gives an absolute relative error of 3.1 and 14%, respectively, for the first and the second setups, while estimating the error between the latter and results from a conventional random fault injection provides error values of up to 75%. Finally, applying our fault injection approach on a more conventional circuit reveals that taking the relative sensitivity difference into account leads to 2.3 times as many errors detected as with random injection. This last result suggests that not taking the relative sensitivity difference into account during emulation can lead to an underestimation of a design sensitivity to radiation.

Soft sensor design for mechanical fault detection in PMSM at variable speed

Abstract This paper presents a soft sensor (SS) used to localize mechanical faults in a Permanent Magnet Synchronous Machine (PMSM) at variable speed. The speed contains crucial information about the fault and the characteristic frequencies sought can be amplified by a proper observer design to improve the detection procedure. On the other hand, all the measurements are expressed as a function of estimated position in order to obtain a speed independent signature. An original experimental setup based on a mechanical fault emulator is proposed to validate the simulation results. Simulations and experimental results show that the proposed method is effective to amplify the single fault signatures and calculate fault indicator at variable speed.