Fast Transient Low-dropout Regulator Research Articles

A Fast Transient Low-Dropout Regulator with High-Power Supply Rejection

With the continuous popularization of portable electronic products in electronic information, aerospace, biomedicine and other fields, low-dropout regulator (LDO) has become an important part of modern power management chips. Compared with other power management modules, it has the advantages of low power consumption, high power supply rejection, and strong anti-noise capability. However, the LDO power tube has a large width-to-length ratio, so when the load changes transiently, the gate of the power tube cannot respond in time, resulting in an overshoot and undershoot of the output voltage and a long recovery time. In this paper, the LDO transient enhancement circuit is designed. When the load changes transiently, the power tube gate capacitor is quickly charged and discharged, which overcomes the overshoot voltage and undershoot voltage. While improving the transient response of traditional LDO, the structure ensures the power supply rejection (PSR) and other performance of the circuit. According to the results, with an input of 2.5 V, the output voltage is regulated to 1.2 V, and PSR is -80 dB. When the load changes by 20 mA in 1 μs, it is stable within 1.2 μs while the undershoot voltage is controlled at 51 mV and the overshoot voltage is controlled at 65 mV.

A fast-transient low-dropout regulator (LDO) with Super Class-AB OTA

This paper presents a low power fast transient low-dropout regulator (LDO) employing a Super Class-AB operational transconductance amplifier (OTA). The proposed structure not only achieve large charging/discharging current at the gate of power transistor but also a gain factor, which not only shows excellent transient performance but also ensures enough line/load regulation. Without adding addition circuit structure, the proposed LDO demonstrates a comprehensive improvement, including enhanced line/load regulation and transient performance, when compared with conventional counterpart, implemented in 0.18 μm CMOS technology, the proposed LDO shows a transient voltage variation of 53 mV at Vout for a load step of 10 μA-200 mA and possesses a line/load regulation of 1.25 mV/V and 100 μV/mA respectively.

A High-Efficiency and Fast-Transient Low-Dropout Regulator With Adaptive Pole Tracking Frequency Compensation Technique

An advanced smooth pole tracking technique for a low dropout (LDO) regulator with a ceramic capacitor is presented in this article. Normally, the dominant pole is at the output of an LDO and becomes load dependent, which may cause a loop stability issue during the whole load-current application range. The proposed frequency compensation methodology with adaptive load resistor control of an error amplifier (EA) alleviates the problem and reduces the dependence of equivalent series resistance of an output capacitor. Moreover, combined with this compensation strategy, an ultrafast EA by utilizing a transconductance enhancement technique is proposed to greatly reduce output voltage spikes as well as response time of the LDO during transient. This circuit has been implemented in a 0.18-μm standard CMOS process and occupies an active chip area of 0.017 mm2. Experimental results show that it can deliver 150 mA load current at 200 mV dropout voltage. Good loop stability and transient responses are easily achieved without degrading other important LDO parameters.

An Inductive Power and Data Telemetry Subsystem With Fast Transient Low Dropout Regulator for Biomedical Implants.

This paper presents a capacitorless low-dropout (LDO) regulator with fast transient response and data reverse telemetry circuit for fully implantable wireless transmission applications. We propose a novel hybrid feedback structure using high-frequency compensation technology to achieve a rapid transient response for the LDO regulator. To reduce the size of the implant and transmit neural recordings through the same coil without interfering with power transmission, the load-shift-key (LSK) modulation technique is adopted for back data telemetry. The proposed implantable chip, fabricated using commercial 0.18 μm complementary metal oxide semiconductor technology, yielded an output power of 15 mW. Under 1.15 V operation voltage, the maximum overshoot and undershoot voltages were less than 45 mV and 55 mV, respectively, for a 15 mA full-load current whose rising and falling time were less than 100 ns. The proposed LSK transceiver uses a digitized demodulator to improve bandwidth efficiency for low carrier frequency operation.

A Fast-Transient Low-Dropout Regulator With Load-Tracking Impedance Adjustment and Loop-Gain Boosting Technique

A low-voltage fast-transient low dropout (LDO) regulator compensated by an off-chip, low-equivalent-series-resistance (ESR), nanorange output capacitor is reported in this brief. The proposed load-tracking impedance adjustment and the loop-gain boosting technique make the proposed LDO regulator have fast response and small voltage spikes. The circuit is implemented by a commercial 0.35- μm CMOS technology. The chip area is 0.032 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The supply voltage ranges from 1.5 to 3 V. The regulated voltage is 1.2 V to provide 0-100 mA. The quiescent current in the no-load condition is 26 μA. A 100-nF low-ESR capacitor is sufficient to stabilize the proposed LDO regulator. The measured voltage spike is 44.9 mV only, and the response time is less than 0.2 μs.