Fast Packet-switched Networks Research Articles

A 2.56-Tb/s multiwavelength and scalable switch-fabric for fast packet-switching networks

We propose an implementation of a terabits-per-second crossbar-equivalent switch-fabric for packet-switching networks. It consists of switch-modules employing semiconductor optical amplifier gates (SOAGs), arrayed waveguide grating routers, and multiple wavelength-channels. It offers large modularity and a small internal loss. The number of SOAGs in a 256/spl times/256 switch-fabric is one-eighth that of a conventional switch-fabric. Scalability up to 2.56 Tb/s is demonstrated by a 10 Gb/s transmission experiment in which the input level into the switch-module was observed to possess a dynamic range of 6 dB.

Optimal multiplexing on a single link: delay and buffer requirements

This paper is motivated by the need to provide per-session quality of service guarantees in fast packet-switched networks. We address the problem of characterizing and designing scheduling policies that are optimal in the sense of minimizing buffer and/or delay requirements under the assumption of commonly accepted traffic constraints. We investigate buffer requirements under three typical memory allocation mechanisms which represent tradeoffs between efficiency and complexity. For traffic with delay constraints we provide policies that are optimal in the sense of satisfying the constraints if they are satisfiable by any policy. We also investigate the tradeoff between delay and buffer optimality, and design policies that are "good" (optimal or close to) for both. Finally, we extend our results to the case of "soft" delay constraints and address the issue of designing policies that satisfy such constraints in a fair manner. Given our focus on packet switching, we mainly concern ourselves with nonpreemptive policies, but one class of nonpreemptive policies which we consider is based on tracking preemptive policies. This class is introduced and may be of interest in other applications as well.

Routing strategies for fast networks

Modern fast packet switching networks are being forced to rethink the routing schemes that are used in more traditional networks. The reexamination is necessitated because in these fast networks switches on the message's route can afford to make only minimal and simple operations. For example, examining a table of a size proportional to the network size is out of the question. We examine routing strategies for such networks based on flooding and predefined routes. Our concern is to get both efficient routing and an even (balanced) use of network resources. We present efficient algorithms for assigning weights to edges in a controlled flooding scheme but show that the flooding scheme is not likely to yield a balanced use of the resources. We then present efficient algorithms for choosing routes along: bfs trees and shortest paths. We show that in both cases a balanced use of network resources can be guaranteed.

Enforcing application-level QoS by frame-induced packet discarding in video communications

Advances in networking are making it feasible to support a wide spectrum of video services over fast packet-switched networks. In this paper, we investigate the problem of providing efficient QoS guarantees for video communication, when they are expressed at the application-level, in terms of video frames, rather than at the network-level, in terms of packets. We propose a simple to implement, yet effective, strategy called frame-induced packet discarding (FIPD), in which, upon detection of loss of a threshold number (determined by an application's video encoding scheme) of packets belonging to a video frame, the network attempts to discard all the remaining packets of that frame. We present extensive, trace-driven performance simulations that demonstrate the efficacy of the FIPD strategy. Networks employing the FIPD strategy exhibit significant increase in the number of video channels that they can support. Towards such networks, using a discrete time Markov chain model of the FIPD strategy, we devise a method for computing the frame loss probabilities of video applications, which then serves as the criterion for admission control: the network admits an incoming application only if the predicted frame loss probability (in the event of admission) does not exceed the frame loss bounds of any of the applications being serviced.

Adaptive isarithmic flow control in fast packet switching networks

We consider the centralized adaptive isarithmic flow control scheme proposed by Mason and Gu (1985) and studied further by Coderre (1989). These previous studies addressed traditional packet switched networks (low speeds). In this paper, the flow control technique is studied in the context of fast packet switching networks. The high transmission rates involved in such networks make it necessary to specifically consider propagation delays. Propagation delay is modeled by M/D//spl infin/ queues on all trunks. The previous studies presented heuristic adaptive algorithms for the controller that attempted to maximize a performance criteria: the product of powers. We present an adaptive algorithm for the controller which is a very good approximation to the optimal operation in a fast packet switching network under heavy traffic. The claim is supported by analytic results (expected operation of system) and Monte Carlo simulation results. While the control architecture has broader applicability, our frame of analysis is product form networks. >

A low complexity video subband coder for ATM

This paper discusses a low complexity, very good visual quality video subband coder fully compatible with ATM networks. The coder is designed to compress an incoming video signal bit-rate by a factor of 9–13 and it is applicable to ‘ Head & Shoulders’ as well as ‘ Full Motion’ sequences. Such results being obtainable in a 17 Mips calculation complexity environment allow the coder implementation on a conventional digital signal processor. The system exploits the characteristics of subband decomposed image through a ‘multiresolution’ quantization methodology. This new resource allocation technique enables the coder to be layered and variable bit-rate. These two properties are essential for optimal use of the coder on a fast packet switching network.

Characterization of a 16-channel optical/electronic selector for fast packet-switched WDMA networks

We report the demonstration of a 16-channel optical/electronic selector for applications in fast packet-switched wavelength division multi-access networks. The selector chip has four differential transimpedance amplifiers with each amplifier shared by four photodetectors, giving a total of 16 channels selected by two stages of MESFET switches. The channel switching time is approximately 10 ns. No appreciable crosstalk is observed from neighboring channels in the first-stage switches, and a 0.35 dB crosstalk penalty is measured through the second-stage switches at a BER of 10/sup -9/ with -20 dBm average optical power in the interference channel. The selector can also be reconfigured as an unswitched four-channel array receiver.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A four-channel monolithic optical/electronic selector for fast packet-switched WDMA networks

We report the characteristics of a four-channel monolithic GaAs optical/electronic selector for applications in fast packet-switched wavelength division multiaccess networks. The selector chip consists of four metal-semiconductor-metal photodetectors sharing a single differential transimpedance amplifier selected by four enhancement-mode MESFET switches. The channel switching time is about 2 ns and no appreciable crosstalk is observed from neighboring channels. >

Unified approaches to integrated-service networks–burst and fast packet switching

The increasing demand for communication services, coupled with recent technological advances in communication media and switching techniques, has resulted in a proliferation of new and expanded services. Currently, networks are needed which can transmit voice, data and video services in an application-independent fashion. Unified approaches employ a single switching technique across the entire network bandwidth, thus allowing services to be switched in an application-independent manner. This paper presents a taxonomy of integrated-service networks, including a look at NISDN, while focusing on unified approaches to integrated-service networks. The two most promising unified approaches are burst and fast packet switching. Burst switching is a circuit switching-based approach which allocates channel bandwidth to a connection only during the transmission of ‘bursts’ of information. Fast packet switching is a packet switching-based approach which can be characterized by very high transmission rates on network links and simple, hard-wired protocols which match the rapid channel speed of the network. Both approaches are being proposed as possible implementations for integrated-service networks. We survey these two approaches, and also examine the key performance issues found in fast packet switching. We then present the results of a simulation study of a fast packet switching network.

About maximum transfer rates for fast packet switching networks

About maximum transfer rates for fast packet switching networks

Simulation of fast packet-switched photonic networks for interprocessor communication

This paper considers the application of time-division multiplexing as an enhancement to the performance of photonic space switching networks, breaking this tie between transmission and switching bandwidths in space-division topologies. In this way better utilization of the photonic switching bandwidth is achieved. Both synchronous and asynchronous TDM are considered. A simulation study is conducted to examine the buffer behavior at input and output stages of two proposed architectures. The interest is in buffer latency and saturation point as functions of the offered load and the multiplexing factor L. The effect of the latter parameter dominates with the single channel fabric. For an N*N fabric, the input buffer singularity is determined by L/N. In the strictly nonblocking fabric, it is shown that for an arbitrarily large switch dimension, delay performance tends to converge for L>2. >

Simulation of fast packet-switched photonic networks for interprocessor communication

Simulation of fast packet-switched photonic networks for interprocessor communication

Link access blocking in very large multi-media networks

This paper is concerned with performance models and approximations for very large, multi-media networks. Blocking is the traditional performance measure in circuit-switched networks, and will remain as such in multi-rate circuit-switched networks. It is also considered a likely performance measure candidate for resource management and dimensioning in broadband fast packet-switched networks, operated under virtual circuit mode. To gain some insight into network-wide blocking phenomena, we study in this paper the basic building block of any network, a single link. Multi-media traffic calls with Poisson arrivals, arbitrarily distributed service times, and different bandwidth requirements (in number of circuits), are offered to a system (link) of finite capacity. A call is rejected when the sharing policy doesn't allow it to be accommodated by the system. Under complete sharing policy, an aggregate state describing the number of occupied circuits is shown to exhibit a product form solution in steady state, when the capacity and traffic intensities become very large asymptotically. This structural property leads to the main result of this paper, an approximation which reduces the computation of the blocking probabilities for the different classes of traffic to the evaluation of a single Erlang formula and the determination of the root of a monotonous polynomial function. We provide comparison curves of the exact blocking probabilities and the approximations for some examples with 3 classes of traffic.

Selective recovery of video packet loss using error concealment

An efficient recovery method using error concealment is proposed for video packet loss in fast packet switching networks. In this method, the receiver detects the damaged picture area caused by packet loss from the structured picture data received, makes error concealments, notifies the transmitter, and continues decoding. The transmitter, having received the notice, calculates the affected picture area in the local decoded picture and continues encoding without using this affected area. In this selective recovery method, video signals are not stopped even if a long propagation delay exists, no additional information is transmitted to error recovery and conventional coding algorithms can be used. The proposed method is suitable for multipoint communication. Simulation results show the affected picture area is localized for a considerable time attesting to the method's effectiveness. >

Experience with the TASSO Data Acquisition System

A coupled system using NORD 10S and NORD 100 computers has been developed for online control of the TASSO experiment at DESY. On one machine data are read from CAMAC, formatted, buffered locally on disk and processed by 168/E emulators before being transferred directly to the DESY IBM complex. A sample of data is sent to the second machine for monitoring and display. A fast packet switching network has been used for making the connection between the NORD computers and has the potential for expansion to include additional processors. This configuration including the operation of the 168/E emulators is described.

PADAC Multi-Microcomputers Basic Building Blocks for Future Control Systems

Based on experience with the PETRA control system a concent for multi-microcomputer arrangements within the PADAC standard has been developed. This setup allows the use of independent microcomputers (based on the TMS 9900) within a group of PADAC crates. Each individual microcomputer executes code from its local memory and has access to all PADAC I/O modules and a common database (256 kbytes of memory) via the shared PADAC bus. The database is assumed to contain at any time the current status of a certain control sub process. A modified version of the SEDAC data acquisition hardware is be used to collect the process status at the necessary refresh rate. The communication with the outside world (operator console, etc.) is accomplished by a fast packet switching network (FPSS3).