Fast Discriminator Research Articles

On novel front-end electronics for the ATLAS BI RPC upgrade at HL-LHC developed in SiGe BiCMOS technology with a high-resolution rad-hard Time-To-Digital converter embedded

The High Luminosity phase of LHC will require a huge improvement on the ATLAS detector in terms of performance, being the entire apparatus operated in much harsher conditions. The BI project is one of the ATLAS Phase-2 approved upgrades, ensuring the demands coming from the physics for the next 20 years. In this framework, a novel dedicated Front-End electronics has been developed, which exploits a BJT-based preamplifier, a fast discriminator and a high resolution (¡ 100 ps) Time-To-Digital converter in SiGe BiCMOS technology, to vastly enhance the detector rate capability. This front-end electronics is integrated for the first time within the detector Faraday cage, largely reducing the effects of spurious noise and allowing a minimum effective charge threshold on the induced signal of 1-2 fC. The integration of the front-end electronics directly within the detector Faraday cage is also permitted by the low power consumption of 15 mW/ch. The RPC coupled with this novel front-end electronics represents a new generation of large area timing detectors, granting a record time resolution of 350 ps on a single gas gap of 1 mm with 1.2 mm electrodes thickness and operated with the ATLAS standard gas mixture. The effect of the extremely low threshold has also an impact on the gas mixture, enabling the usage of eco-friendly gas mixtures which would not be usable elsewise. The latest performance of this newly developed front-end electronics along with the results achieved with RPC detector coupled with it will be shown.

Analog Front-End for the Readout of LGAD-Based Particle Detectors

This paper presents an analog front-end channel for the readout of Low Gain Avalanche Diodes (LGADs) based particle detectors for the next generation of space-borne experiments. The circuit has been designed in a 65 nm CMOS technology. The charge generated by the detector is integrated by a Charge Sensitive Amplifier (CSA) with dynamic signal compression feature to achieve improved noise performance, along with enhanced time resolution capabilities over the wide range of input charge to be detected (from 45fC to 16pC). An RC-CR shaper with selectable shaping time, a fast discriminator and a Time-to-Amplitude Converter (TAC) complete the readout circuit. An SNR around 300, together with a time resolution of slightly below 60ps, is achieved in post-layout simulations.

Improved electric-thermal-aging multi-physics domain coupling modeling and identification decoupling of complex kinetic processes based on timescale quantification in lithium-ion batteries

Unraveling the kinetic behavior inside the battery is essential to break through the limitations of mechanistic studies and to optimize the control of the integrated management system. Given this fact that the battery system is multi-domain coupled and highly nonlinear, an improved lumped parameter multi-physical domain coupling model is first developed to capture the electrical, thermal and aging characteristics of the battery in this paper. On this basis, an adaptive multi-timescale decoupled identification and estimation strategy is proposed based on the quantified timescale innovation, which realizes the online monitoring of the battery state and the accurate identification of the model parameters. The specific idea is that the decoupled identification of kinetic parameters inside the cell, the terminal voltage prediction and the real-time monitoring of the internal temperature with the online estimation of the available capacity are distinguished under different timescales. Meanwhile, the response time characteristic of the different kinetics is extracted and analyzed as a distinction between the coupled internal electrochemical processes. In this idea, four functionally different sub-observers are developed independently. Significantly, adaptive time-scale driven methods designed based on the fundamental timescale of the system, the amount of variation of the state of charge, and the amount of transfer charge are used separately for the observer implementation at different timescales. In addition, the coupling of the fast and slow kinetic parameter discriminators is achieved by diffusion voltage, and the internal temperature observer as well as the available capacity observer are coupled to each other based on the estimation results. Experimental results for two long-time operating conditions at 5, 25 and 45 °C show that the proposed strategy has fast convergence and reliable accuracy in monitoring the battery state characteristics. Compared with the traditional fixed timescale algorithm, the proposed multi-physics domain coupling modeling strategy based on independent timescale driven design is more competitive in practical embedded applications.

NTIMP1—A Fast Pulse Readout Chip With 1.2 V Power Supply Applied to the Diamond Detector in HIAF

A very fast pulse readout ASIC, NTIMP1, with 1.2 V power supply is presented in this work. It is going to be used as front-end electronics (FEE) for reading out the diamond detector signals in the TOF (Time of Flight) wall of RIBLL2 experiment of the High Intensity Heavy Ion Accelerator Facility (HIAF), China. So that an 8-channel fast front-edge readout chip named as NTIMP1 is proposed in this work. Each channel of NTIMP1 has a high-bandwidth preamplifier (with adjustable thresholds) dealing with differential current input, a fast hysteresis discriminator, and a LVDS (Low-Voltage Differential Signaling) module ensuring long-distance signal transmission. Fabricated with 0.13 μm standard CMOS Technology, NTIMP1 can get an input ranging from 2 fC to 2000 fC and the input impedance of the preamplifier can be adjusted externally with an off-chip resistor, so as to match with the electrode impedance of diamond detector. The bandwidth of the preamplifier is 495.5 MHz, which allows a very short signal peaking time of no more than 1 ns. The jitter of the leading edge is lower than 15 ps with 100 fC input charge suggesting that NTIMP1 is suitable for high-resolution TOF measurement as well as time-slewing correction.

HGCROC2: the front-end readout ASICs for the CMS High Granularity Calorimeter

The CMS High-Granularity Calorimeter (HGCAL) imposes extremely challenging specifications for the front-end electronics: high dynamic range, low noise, high-precision time information and low power consumption, as well as the need to select and transmit trigger information with a high transverse and longitudinal granularity. HGCROC2 is the second prototype of the readout chip embedding almost all the final functionalities. It has 72 channels of the full analog chain: low noise and high gain preamplifier and shapers, a 10-bit 40 MHz SAR-ADC which provides the charge measurement over the linear range of the preamplifier, after the preamplifier saturation a discriminator and TDC provide the charge information from ToT (200 ns dynamic range and 50 ps binning), and a fast discriminator and TDC provide timing information to 25 ps accuracy. This paper reports on the performance in terms of noise, charge and timing, the DAQ and Trigger paths, as well as results from radiation qualification with total ionizing dose (TID) and heavy ions for single-event effects (SEE).

HGCROC3: the front-end readout ASIC for the CMS High Granularity Calorimeter

For the CMS High Granularity Calorimeter (CE), the final version of the 72-channel front-end ASIC (HGCROC3) was submitted in December 2020. HGCROC3 includes low-noise/high-gain preamplifiers/shapers and a 10-bit 40 MHz successive approximation ADC (SAR-ADC) that provide the charge measurement over the linear range of the preamplifier. In the saturation range, a discriminator and a time-to-digital converter (TDC) provide the charge information from the time over threshold (ToT; 200 ns dynamic range, 50 ps binning). A fast discriminator and another TDC provide timing information to 25 ps accuracy. The chip embeds all necessary ancillary services: bandgap circuit, PLL, threshold DACs. We present the experimental results on the latest and final version (HGCROC3) received in April 2021.

Performance study of HGCROC-v2: the front-end electronics for the CMS High Granularity Calorimeter

The High Granularity Calorimeter (HGCAL), presently being designed by the Compact Muon Solenoid collaboration (CMS) to replace the existing endcap calorimeters for the High Luminosity phase of the LHC (HL-LHC), will feature unprecedented transverse and longitudinal readout and triggering segmentation for both electromagnetic and hadronic sections. The requirements for the front-end electronics are extremely challenging, including high dynamic range (0–10 pC), low noise (0∼ 200 electrons), high-precision timing information in order to mitigate the pileup effect (25 ps binning) and low power consumption (∼ 15 mW/channel). The front-end electronics will face a harsh radiation environment which will reach 200 Mrad at the end of life. It will work at a controlled temperature of 240 K. HGCROC-v2 is the second prototype of the front-end ASIC. It has 72 channels of the full analog chain: low noise and high gain preamplifier and shapers, and a 10-bit 40 MHz SAR-ADC, which provides the charge measurement over the linear range of the preamplifier. In the saturation range of the preamplifier, a discriminator and TDC provide the charge information from TOT (Time Over Threshold) over 200 ns dynamic range using 50 ps binning. A fast discriminator and TDC provide timing information to 25 ps accuracy. Both charge and timing information are kept in a DRAM memory waiting for a Level 1-trigger decision (L1A). At a bunch crossing rate of 40 MHz, compressed charge data are sent out to participate in the generation of the L1-trigger primitives. We report on the performances of the chip in terms of signal-to-noise ratio, charge and timing, as well as results from radiation qualification with total ionizing dose (TID).

Additional aperture detectors of gamma-telescope GAMMA-400 calibrations on synchrotron “PAKHRA”: possibility of temporal profiles fractal analysis

GAMMA-400 (Gamma Astronomical Multifunctional Modular Apparatus) will be the new generation satellite gamma-observatory. The gamma-ray telescope GAMMA-400 consists of anticoincidence system (top and lateral sections - ACtop and AClat), the converter-tracker (C), time-of-flight system (two sections S1 and S2), position-sensitive calorimeter CC1, electromagnetic calorimeter CC2, scintillation detectors of the calorimeter (S3 and S4) and lateral detectors of the calorimeter LD.Three apertures provide events registration both from upper and lateral directions. The main aperture provides the best angular (all double (X, Y) tracking coordinate detectors layers information analysis) and energy resolution (energy deposition in the all detectors studying). The main aperture created firstly due to converter-tracker (C): gammas converted in tungsten conversion foils are registered. Triggers in the main aperture will be formed using information about particle direction provided by time of flight system and presence of charged particles or backsplash signal formed according to analysis of energy deposition in combination of both layers anticoincidence systems ACtop and AClat individual detectors. Other two apertures used for observation of transient events do not require best angular resolution as gamma-ray bursts and solar flares both from upper and lateral directions. Additional aperture allows particles registering from upper direction, which don’t interact with converter-tracker and don’t formed TOF signal. Particles detection in additional aperture starts with signal of CC1 fast discriminators in anticoincidence with TOF. Energy band for gammas registration in this aperture is similar to the main one. In the lateral aperture low energy (0.2-100 MeV) photons classified by using simple anticoincidence signals from the individual detectors of LD and CC2. Higher energies γ-quanta (E>100 MeV) recognized using energy deposition analysis in the individual detectors of S3, S4, LD and CC2. Prototype of additional aperture functioning of GAMMA-400 contains two detectors. One of them AC/LD prototype based on BC-408 scintillator with dimensions of 128x10x1 cm3. Other is CC1 prototype composed of CsI(Tl) crystal with dimensions of 33x5x2 cm3. The positron beam with energies 100-300 MeV was used for calibration of prototypes of GAMMA-400 detectors on synchrotron “PAKHRA”. We calculate fractal dimension of temporal profiles measured during calibrations of AC/LD and CC1 prototypes. Preliminary results are 1.50±0.05 and 1.48±0.08 correspondingly. This is similar to Poisson statistics or Erlang one with coefficient up to 10.

WaveDAQ: An highly integrated trigger and data acquisition system

The WaveDAQ is a full custom, compact and highly integrated trigger and data acquisition system. Despite the decisive urge from the MEG II experiment at PSI aiming at a sensitivity of 6×10−14 on the μ→eγ decay, it is a general purpose device suited for small and medium-sized applications in the range from 16 to about 10 000 channels. It exploits the performance of the DRS4 waveform digitiser with a sampling speed programmable from 1 to 5 GSPS; each input channel can supply HV to arrays of SiPMs and provides a front-end amplification with gains chain in the range from 0.5 up to 100 and GHz bandwidth. Input signals are, in parallel to the DRS4, digitised at 80 MSPS and used in an FPGA-based trigger; fast discriminators associated to each input channel are also used for online reconstruction. This paper presents the WaveDAQ design principles and the results obtained by a demonstrator in the MEG II pre-engineering run in fall 2017 with a homogeneous LXe detector and a plastic scintillation detector both readout by SiPMs and in the tests associated to the ΔE-TOF prototype of the FOOT detector.

A Front-End Channel in 65 nm CMOS for Pixel Detectors at the HL-LHC Experiment Upgrades

A front-end channel prototype for pixel detectors has been designed for the upgrades of the HL-LHC experiments. The circuit is based on a Krummenacher feedback network to continuously reset the charge sensitive amplifier and on a fast threshold discriminator to implement a time-over-threshold (ToT) method and perform amplitude measurement. The front-end circuit was developed in a 65 nm CMOS technology and takes an overall area not exceeding 1250 $\mu \text {m}^{2}$ , i.e., half of the overall pixel area. The current consumption per channel is around 4 $\mu \text {A}$ at $VDD=1.2$ V. A very small charge sensitivity dispersion was detected in the set of characterized samples. An equivalent noise charge of 120 e− was found for a detector capacitance of 100 fF. The response of the channel is compatible with the speed requirements of the foreseen application in the innermost layers of the CMS pixel detector.

Analog front-end design of the STS/MUCH-XYTER2—full size prototype ASIC for the CBM experiment

The design of the analog front-end of the STS/MUCH-XYTER2 ASIC, a full-size prototype chip for the Silicon Tracking System (STS, based on double-sided silicon strip sensors) and Muon Chamber (MUCH, based on gas sensors) detectors is presented. The ASIC contains 128 charge processing channels, each built of a charge sensitive amplifier, a polarity selection circuit and two pulse shaping amplifiers forming two parallel signal paths. The first path is used for timing measurement with a fast discriminator. The second path allows low-noise amplitude measurement with a 5-bit continuous-time flash ADC. Different operating conditions and constraints posed by two target detectors' applications require front-end electronics flexibility to meet extended system-wise requirements. The presented circuit implements switchable shaper peaking time, gain switching and trimming, input amplifier pulsed reset circuit, fail-safe measures. The power consumption is scalable (for the STS and the MUCH modes), but limited to 10 mW/channel.

Investigation of the time performance of a LYSO array for TOF-PET**Supported by National Natural Science Foundation of China (10775149, 10805049), the Fundamental Research Funds for the Central Universities (2013NT10)

Positron Emission Tomography (PET) using time-of-flight information, which can greatly improve the quality of the reconstructed image, has recently become an exciting topic. In this work, 3.2 mm×3.2 mm×25 mm finger-like LYSO crystals were used to make a 5×5 array, coupled to the Hamamatsu H8500 photomultiplier tube (PMT) as a detector. A fast leading-edge discriminator was designed for the LYSO-H8500 detector. Average coincidence time resolution FWHM of 330 ps was obtained for the LYSO detector with a reference BaF2 detector, whose time resolution for 511 keV γ-rays was FWHM 150 ps. Time resolution FWHM of 294 ps was calculated for the LYSO detector, and coincidence time resolution of FHWM 415 ps can be expected for two identical LYSO detectors.

Frontend electronics for high-precision single photo-electron timing using FPGA-TDCs

The next generation of high-luminosity experiments requires excellent particle identification detectors which calls for Imaging Cherenkov counters with fast electronics to cope with the expected hit rates. A Barrel DIRC will be used in the central region of the Target Spectrometer of the planned PANDA experiment at FAIR. A single photo-electron timing resolution of better than 100ps is required by the Barrel DIRC to disentangle the complicated patterns created on the image plane. R&D studies have been performed to provide a design based on the TRB3 readout using FPGA-TDCs with a precision better than 20ps RMS and custom frontend electronics with high-bandwidth pre-amplifiers and fast discriminators. The discriminators also provide time-over-threshold information thus enabling walk corrections to improve the timing resolution. Two types of frontend electronics cards optimised for reading out 64-channel PHOTONIS Planacon MCP-PMTs were tested: one based on the NINO ASIC and the other, called PADIWA, on FPGA discriminators. Promising results were obtained in a full characterisation using a fast laser setup and in a test experiment at MAMI, Mainz, with a small scale DIRC prototype.

A Reconfigurable Instrument System for Nuclear and Particle Physics Experiments

We developed a reconfigurable nuclear instrument system (RNIS) that could satisfy the requirements of diverse nuclear and particle physics experiments, and the inertial confinement fusion diagnostic. Benefiting from the reconfigurable hardware structure and digital pulse processing technology, RNIS shakes off the restrictions of cumbersome crates and miscellaneous modules. It retains all the advantages of conventional nuclear instruments and is more flexible and portable. RNIS is primarily composed of a field programmable hardware board and relevant PC software. Separate analog channels are designed to provide different functions, such as amplifiers, ADC, fast discriminators and Schmitt discriminators for diverse experimental purposes. The high-performance field programmable gate array could complete high-precision time interval measurement, histogram accumulation, counting, and coincidence anticoincidence measurement. To illustrate the prospects of RNIS, a series of applications to the experiments are described in this paper. The first, for which RNIS was originally developed, involves nuclear energy spectrum measurement with a scintillation detector and photomultiplier. The second experiment applies RNIS to a G-M tube counting experiment, and in the third, it is applied to a quantum communication experiment through reconfiguration.

PETA4: a multi-channel TDC/ADC ASIC for SiPM readout

The PETA4 ASIC is the latest member of a family of chips targeted mainly at the readout of Silicon Photomultipliers in PET, with possible use in other detector applications. PETA4 houses 36 channels on a 5 × 5mm2 die and is fabricated in the UMC 180nm technology.It uses bump bonds with a convenient pitch of ≈ 270μm to allow the construction of very compact modules at moderate substrate cost. The chip requires nearly no external components by integrating everything (PLL loop filter, bandgap reference, bias DACs,…) on chip. Power consumption is ⩽ 40mW per channel, depending on digital speed and bias settings.Every channel has two independent frontends: an established differential amplifier which has shown to be insensitive to pickup in the target application of PET/MRI, and a single-ended frontend with very low input impedance (Zin ≈ 7Ω) for high channel count operation. A fast discriminator with tunable threshold and a noise of ⩽ 300μV self-triggers time stamping with a bin width of 50ps as well as an integratorwith programmable integration time. The amplitude signal is converted by a ≈ 9-bit SAR ADC. After conversion, events with sufficient amplitude arequeued for serial readout. The previous chip version PETA3 has achieved a CRT time resolution of ≈ 200ps when reading out scintillation lightfrom a 3 × 3×5mm3 LYSO crystal coupled at room temperature to a 3 × 3mm2 SiPM from FBK. Energy resolution for LYSO is ≈ 12.5%FWHM. LYSO crystals of 1.3mm size could be clearly identified with SiPMs of 4 × 4mm2 when using a light spreader.The architecture of PETA4 and its performance in the lab and with SiPMs will be presented.

Particle tracking at 4 K: The Fast Annihilation Cryogenic Tracking (FACT) detector for the AEgIS antimatter gravity experiment

The AEgIS experiment is an international collaboration with the main goal of performing the first direct measurement of the Earth's gravitational acceleration on antimatter. Critical to the success of AEgIS is the production of cold antihydrogen (H¯) atoms. The FACT detector is used to measure the production and temperature of the H¯ atoms and for establishing the formation of a H¯ beam. The operating requirements for this detector are very challenging: it must be able to identify each of the thousand or so annihilations in the 1ms period of pulsed H¯ production, operate at 4K inside a 1T solenoidal field and not produce more than 10W of heat. The FACT detector consists of two concentric cylindrical layers of 400 scintillator fibres with a 1mm diameter and a 0.6mm pitch. The scintillating fibres are coupled to clear fibres which transport the scintillation light to 800 silicon photomultipliers. Each silicon photomultiplier signal is connected to a linear amplifier and a fast discriminator, the outputs of which are sampled continuously by Field Programmable Gate Arrays (FPGAs).In the course of the developments for the FACT detector we have established the performance of scintillating fibres at 4K by means of a cosmic-ray tracker operating in a liquid helium cryostat. The FACT detector was installed in the AEgIS apparatus in December 2012 and will be used to study the H¯ formation when the low energy antiproton physics programs resume at CERN in the Summer of 2014. This paper presents the design requirements and construction methods of the FACT detector and provides the first results of the detector commissioning.

A Front-End electronics board for single photo-electron timing and charge from MaPMT

A Front-End (FE) design based on commercial operational amplifiers has been developed to read-out signals from a Multianode PhotoMultiplier Tube (MaPMT). The overall design has been optimised for single photo-electron signal from the Hamamatsu H8500. The signal is collected by a current sensitive preamplifier and then it is fed into both a ECL fast discriminator and a shaper for analog output readout in differential mode. The analog signal and the digital gates are then registered on VME ADC and TDC modules respectively. Performances in terms of linearity, gain and timing resolution will be discussed, presenting results obtained on a test bench with differentiated step voltage inputs and also with a prototype electronic board plugged into the H8500 PMT illuminated by a picosecond laser.

Front End ASIC design for SiPM readout

A Front End ASIC for the readout of Silicon Photo-Multipliers is presented with the following features: wide dynamic range, high speed, multi channel, low input impedance current preamplifier, low power (7mW per channel), DC coupled input with common mode voltage control and separated timing and charge signal output.A detailed description of the SiPM modeling and parameter extractionis also included allowing the emulation of the signal generated bydifferent commercial devices in the design simulation stage. Currentprototype is the first step for a more complex mixed signal designincluding more channels, analog processing and digital outputs, thusreducing power consumption and increasing integration. This prototypeincludes basic blocks for 3 channels with: preamplifier with twoseparate signal paths and fast current discriminator with digitaloutput.

Fast frequency tracking

A method of periodical signal frequency tracking by the frequency-locked loops is proposed. Increasing of frequency adjustment accuracy is achieved by using of a new fast frequency discriminator, based on estimates of an instantaneous frequency. Reasonability of an input signal pre-filtering in case of nonlinear distortions, harmonics interferences and strong noise is proved.

A CMOS front-end for MPPC-based detectors aimed to TOF applications with fast discriminator, adjustable arming threshold and constant-fraction functionality

We have designed and realized a Front-End chip for MPPC in standard CMOS 0.35μm technology. The channel presents a low input impedance in order to reduce as much as possible the recovery time of the sensor. This is achieved using the current domain for processing signals through the current conveyors (CCII) as building blocks of the channel. A current feed-back with low-pass filter has also been used to realize a sensitive improvement of the correction of the pile-up problem, in case of high repetition rate events. An independent arming threshold is available for each channel, providing the selection of the event through the peak level (proportional to the number of simultaneously hit pixels) reached by the signal. A constant-fraction functionality is present in order to reduce the well know time-walk problem. The delay in the correspondent branch is obtained by using an additional CCII block. The digital output of the discriminator channel has adjustable time width. The pilot chip is made up of five channels. All the values of the independent thresholds are stored in 10−bit registers as well as the values of the trigger output width and the main polarization current of the CCII blocks. All the registers are writable from a standard three-wire SPI. These features make the chip fully self-consistent. In this work we present and discuss the simulation results together with the preliminary test performed.