Fair Reachability Research Articles

An approach to cyclic protocol validation

In this paper, the notion of fair reachability is generalized to cyclic protocols with more than two processes, where all the processes in a protocol are connected via a unidirectional ring and each process might contain internal transitions and can be non-deterministic. We identify ‘indefiniteness’ as a new type of logical error due to reachable internal transition cycles. By properly incorporating internal transitions into the formulation, we show that, with a few modifications, all the previous results established for cyclic protocols without non-deterministic and internal transitions still hold in the augmented model. Furthermore, by combining fair progress and maximal progress during state exploration, we prove that the following three problems are all decidable for Q, the class of cyclic protocols with finite fair reachable state spaces: (1) global state reachability; (2) abstract state reachability; and (3) execution cycle reachability. In the course of the investigation, we also show that detection of k-indefiniteness and k-livelock are decidable for Q.

Decidability of a class of dual communicating finite state machines

A number of techniques have been proposed to validate systems of communicating machines which exchange exclusively messages through FIFO channels. The reachability analysis is a well-known and most popular technique implemented in several tools of validation. Two majors questions are discussed : the finiteness of the reachability graph and the state explosion problem. In this paper we clarify a restricted class of dual machines and its applicability of real protocols. Our investigation at the first time concern sufficient conditions to ensure the finiteness of the reachability graph. In the second part of the paper we confirm the results using the fair reachability analysis in which global states are generated by forcing the two machines in equal speeds.

Generalized fair reachability analysis for cyclic protocols

In this paper, the notion of fair reachability is generalized to cyclic protocols with n/spl ges/2 machines. It is shown that each fair reachable state is of equal channel length and each deadlock state is fair reachable. As a result, deadlock detection is decidable for P, the class of cyclic protocols whose fair reachable state spaces are finite. The concept of simultaneous unboundedness is defined and the lack of it is shown to be a necessary and sufficient condition for a protocol to be in P. Through finite extension of the fair reachable state space, it is also shown that detection of unspecified receptions, unboundedness, and nonexecutable transitions are all decidable for P. Furthermore, it is shown that any protocol in P is logically correct if and only if there is no logical error in its fair reachable state space. This study demonstrates that for the class P, our generalized fair reachability analysis technique not only can achieve substantial state reduction but also maintains very competitive logical error coverage. Therefore, it is a very useful technique to prove logical correctness for a wide variety of cyclic protocols.

PROSPEC: an interactive programming environment for designing and verifying communication protocols

The PROSPEC software environment for designing and verifying communication protocols is described. It integrates several tools that implement methods for protocol verification and construction (i.e., fair reachability analysis, multiphase construction, and protocol projection). The system provides a unified graphical interface to facilitate the application of these methods and creates an interactive environment for specifying, verifying, and designing communication protocols. PROSPEC was used successfully to design and verify versions of BSC, X.21, X.25, and Telnet document transfer protocols. >

Modalities for model checking: branching time logic strikes back

We consider automatic verification of finite state concurrent programs. The global state graph of such a program can be viewed as a finite (Kripke) structure, and a model checking algorithm can be given for determining if a given structure is a model of a specification expressed in a propositional temporal logic. In this paper, we present a unified approach for efficient model checking under a broad class of generalized fairness constraints in a branching time framework extending that of Clarke et al. (1983). Our method applies to any type of fairness expressed in a certain canonical form. Almost all ‘practical’ types of fairness from the literature, including the fundamental notions of impartiality, weak fairness, and strong fairness, can be succintly written in our canonical form. Moreover, our branching time approach can easily be adapted to handle types of fairness (such as fair reachability of a predicate) which cannot even be expressed in a linear temporal logic. We go on to argue that branching time logic is always better than linear time logic for model checking. We show that given any model checking algorithm for any system of linear time logic (in particular, for the usual system of linear time logic) there is a model checking algorithm of the same order of complexity (in both the structure and formula size) for the corresponding full branching time logic which trivially subsumes the linear time logic in expressive power (in particular, for the system of full branching time logic CTL *). We also consider an application of our work to the theory of finite automata on infinite strings.

Protocol validation by fair progress state exploration

Abstract Consider a network of two communicating finite state machines that exchange messages over two one-directional, unbounded, FIFO channels. The fair reachability graph of such a network is a directed graph whose vertices correspond to global states (of the network) that are reachable by forcing the two machines in the network to progress in equal speeds. It is shown earlier that if the fair reachability graph of a given network is finite, then it can be used to decide whether the communication of this network is free from deadlocks and unspecified receptions. In this paper, we complement this result by showing that if the fair reachability graph of a given network is finite, then it can be used to decide wether the communication of this network is bounded. Moreover, if the communication is found to be bounded, then the finite fair reachability graph can be also used to compute the smallest possible capacities for the two channels in the network.

Fairness and related properties in transition systems ? a temporal logic to deal with fairness

In this paper we propose a notion of fairness for transition systems and a logic for proving properties under the fairness assumption corresponding to this notion. We start from an informal characterization of the unfairness as the situation where some event becomes possible infinitely often but has only a finite number of occurrences, which induces various definitions of fairness by considering different classes of events. It results from the comparison of these definitions that the concept of fairness which is useful is "fair reachability" of a given set of states P in a system, i.e. reachability of states of P when considering only the computations such that if, during their execution, reaching states of P is possible infinitely often, then states of P are visited infinitely often. This definition of fairness suggests the introduction of a branching time logic FCL, the temporal operators of which express, for a given set of states P, the modalities "it is possible that P" and "it is inevitable that P" by considering fair reachability of P. The main result is that, given a transition system S and a formula f of FCL expressing some property of S under the assumption of fairness, there exists a formula f? belonging to a branching time logic CL such that: f is valid for S in FCL iff f? is valid for S in CL. This result shows that proving a property under the assumption of fairness is equivalent to proving some other property without this assumption and that the study of FCL can be made via the "unfair" logic CL, easier to study and for which several results already exist. Finally, the proposed notion of fairness is compared to other related notions such as the absence of livelock, the absence of starvation and the finite delay property.