Semiconductor Failure Analysis Research Articles

Design and manufacturing of aspherical GaAs-SILs for a versatile optical semiconductor failure analysis system

In this study, we have developed an aspherical solid immersion lens (SIL) made of gallium arsenide (GaAs) for semiconductor failure analysis. A SIL is an optical component to dramatically increase the numerical aperture and the spatial resolution of a microscopy system by attaching it to the backside of the device-under-test. To further enhance the spatial resolution of the optical microscopy system, a shorter wavelength light source has also been introduced. In the past, we have developed a spherical SIL made of silicon (Si), which is the same material as the device under test. However, Si is not transparent for wavelengths shorter than around 1100 nm. To enable the use of a SIL at shorter wavelengths, we chose GaAs as SIL material, which is transparent at shorter wavelengths than Si and has a refractive index very close to that of Si. However, a spherical GaAs SIL features a more pronounced spherical aberration due to the difference in refractive index between the device-under-test (Si) and that of the SIL (GaAs) deteriorating the optical resolution of the microscopy system. We have therefore designed an aspherical GaAs-SIL which makes it possible to correct spherical aberration. We applied diamond tooling as a technique for manufacturing the SIL shape with a required surface irregularity below 100 nm peak-to-valley, resulting in a diffraction limited performance of the optical system for semiconductor failure analysis with a performance at around 0.18 μm cutoff.

Grad-CAM을 활용한 EfficientNetV2 기반 웨이퍼 맵 불량분석 연구

In semiconductors, various defect patterns appear on the wafer map due to problems in the design and manufacturing process. Analysis of generated defect patterns will reduce the rate of defects and enable the production of high-quality semiconductors. Considering the number of semiconductors produced, performing defect analysis by human resources is inefficient. Recently, as hardware performance has improved, high-performance deep learning models have been designed. These models show high performance in image classification and have advantages in terms of processing speed. Therefore, this paper used EfficientNetV2 designed to achieve maximum efficiency with few parameters for semiconductor failure analysis. Identifying the location of defects is a critical element of defect analysis, not just classifying defect patterns. Therefore, in this study, we used Grad-CAM to identify the classification of defect patterns and their approximate location. Wafer map dataset is difficult to collect as data includes defects in manufacturing companies

Failure Analysis from a Customer Point of View

Abstract This column addresses the different perspectives of providers and customers of semiconductor failure analysis laboratories. The columnist, after having seen both sides of the electronics industry, as a supplier and customer, sheds light on how the two sides interact when entangled with reliability issues and failures.

Contact metalens for high-resolution optical microscope in semiconductor failure analysis.

The continuous downscaling of electronic devices requires higher-resolution optical microscopic images for semiconductor failure analysis (FA). However, a part of the diffracted light from the measuring pattern in the silicon (Si) substrate cannot be collected due to the total internal reflection (TIR) at the interface between the Si substrate and air. We propose a metalens suitable for FA that improves resolution of optical microscopic images by collecting beyond the critical angle of TIR at the interface. For the proof of concept, we integrated the fabricated metalens into the optical setup of FA and acquired optical microscopic images of FA that clearly show improved resolution.

Faster and More Accurate Failure Analysis: Circuit Editing and Short Localization Performed at Same Tilt Angle using Multiple Techniques

Abstract A recent trend in semiconductor failure analysis involves combining the use of different tools and techniques in order to acquire more accurate data at a faster rate. This article describes a new workflow that combines FIB, GIS, and nanoprobing, all performed at the same FIB tilt position. It also provides two examples in which the workflow is used.

Ultrasonic beam induced resistance change (SOBIRCH) method for failure analysis of semiconductor devices encapsulated by mold resin

In the process of the failure analysis for semiconductor devices, various optical methods are applied as techniques to localize faults of the semiconductor devices. Conventional optical techniques often require the decapsulation of the mold resin, since the mold resin is not optically transparent. As a new fault localization technique requiring no decapsulation, the authors are proposing the ultrasonic beam induced resistance change (SOBIRCH) method based on a heating by focused ultrasonic beam. In this report, the signal intensity of the SOBIRCH method for the capsulated samples was discussed through the experimental and the theoretical approaches. By comparing the experiment and the numerical analysis, it was suggested that a certain thickness of the thin mold resin can enhance the intensity of the SOBIRCH signal. Additionally, an expected effect of the standing wave in the thin mold resin was calculated, and a method to make use of the standing wave was proposed.

Electron-beam radiation induced degradation of silicon nitride and its impact to semiconductor failure analysis by TEM

By in-situ transmission electron microscopy (TEM), we performed a detailed study on the electron-beam radiation damage to nanostructured silicon nitride thin-film process layers in a typical semiconductor NVM device. It was found that high-dose electron-beam radiation at 200 kV led to rapid degradation of silicon nitride process layers, i.e. thin-downing of nanostructured silicon nitride, inter-diffusion of O and N, the formation of bubble-like defects and segregation of N at neighbouring interfaces. Further detailed analysis revealed that radiation-induced modification in the microstructure and chemical composition of silicon nitride layers could be ascribed to the electron radiation induced knock-on damage and ionization damage. The radiation enhanced diffusion (RED) accounted for the continuous thin-down of the nitride process layer and the formation of bubble-like defects in thick nitride spacer process layers. The work well demonstrated the electron-beam sensitivity of nanostructured silicon nitride materials in the semiconductor devices, and thus may give useful information about electron-dose control during TEM failure analysis of the semiconductor devices containing nanostructured silicon nitride process layers.

3-D X-Ray Imaging With Nanometer Resolution for Advanced Semiconductor Packaging FA

As the complexity and interconnect density of advanced semiconductor packages increase, failure analysis and root cause determination are also facing new challenges and higher requirements. The 3-D X-ray microscopy, enabling nondestructive defect imaging and enhanced navigation for failure analysis, is considered a key method to fulfill these requirements. This technique results in a short time to result and high success failure analysis yield. After a short introduction into the basic principles of laboratory-based X-ray tomography, two different approaches of X-ray investigations are discussed. The author demonstrates the capabilities of the individual techniques and gives an outlook into future failure analysis opportunities. This includes the recently developed application using 3-D X-ray imaging for back-end-of-line and chip-package-interaction features.

3D analysis of semiconductor devices: A combination of 3D imaging and 3D elemental analysis

3D analysis of semiconductor devices using a combination of scanning transmission electron microscopy (STEM) Z-contrast tomography and energy dispersive spectroscopy (EDS) elemental tomography is presented. 3D STEM Z-contrast tomography is useful in revealing the depth information of the sample. However, it suffers from contrast problems between materials with similar atomic numbers. Examples of EDS elemental tomography are presented using an automated EDS tomography system with batch data processing, which greatly reduces the data collection and processing time. 3D EDS elemental tomography reveals more in-depth information about the defect origin in semiconductor failure analysis. The influence of detector shadowing and X-rays absorption on the EDS tomography's result is also discussed.

An Advanced Impedance Calibration Method for Nanoscale Microwave Imaging at Broad Frequency Range

A new calibration method for nanoscale complex impedance imaging with the scanning microwave microscope is presented, which allows to calibrate the complete frequency range in a short automated procedure. The vector network analyzer and the corresponding electronically switched calibration capabilities in combination with time domain gating and microwave network modeling are used to de-embed the full system. The entire calibration requires not more than 5 min and the acquisition of one single electrostatic force microscopy approach curve. In order to demonstrate the broadband capabilities, calibrated approach curves at various frequencies are presented. Nano-Schottky diodes on a semiconductor substrate as well as biological cells were measured to demonstrate that the sample conductance and susceptance are in agreement with the theoretical expectations for the samples. This advanced workflow of quantitative impedance calibration may have many applications in the fields of semiconductor failure analysis, 2-D materials, and biological samples in their native liquid environment.

Rapid imaging of misfit dislocations in SiGe/Si in cross-section and through oxide layers using electron channeling contrast

Electron channeling contrast imaging (ECCI) is emerging as a technique for rapid and high-resolution characterization of individual crystalline defects in a scanning electron microscope. However, the application of ECCI to semiconductor materials has been limited to bare samples in plan-view geometry. In this paper, two modalities of this technique are demonstrated with relevance to semiconductor manufacturing and failure analysis: (1) The use of ECCI to reveal misfit dislocation defects along a cleaved cross-section of a SiGe compositionally graded buffer grown on Si and (2) plan-view imaging of misfit dislocations in metamorphic SiGe/Si layers covered by amorphous oxide layers, where the partial loss of contrast due to the oxide layers is quantified and the effect of the beam accelerating voltage is studied. These results demonstrate the power of ECCI in inspecting crystallographic defects non-destructively over large areas, which is highly desirable for substrate quality control in manufacturing of products based on crystalline materials.

Key Issues for Implementing Smart Polishing in Semiconductor Failure Analysis

“Industry 4.0” has become the future direction of manufacturing industry. To prepare for this upgrade, it is important to study the automation of semiconductor failure analysis. In this paper, the sample polishing activity was studied for upgrading to a smart polishing process. Two major issues were identified in implementing the smart polishing process: the optimization of current polishing recipes and the capability of making decisions based on live feedback. With the help of Solver add-in, the current polishing recipes were optimized. To make decisions based on live images captured during polishing, strategies were explored based on finger polishing process study. Our investigation showed that a grey scale line profile analysis on images can be used to build the vision capability of our smart polishing system, on which a decision- making capability can be developed.

Superconducting Single Photon Detector Enables Time-Resolved Emission Testing of Low Voltage Scaled ICs

Abstract Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

Application of Fast Laser Deprocessing Techniques on large cross-sectional view area sample with FIB-SEM dual beam system

Cross-sectional analysis is one of the important areas for physical failure analysis. Focus Ion Beam (FIB) and mechanical polish sample preparation are commonly used and necessary techniques in the semiconductor industry and Failure Analysis (FA) Company (Wills and Perungulam, 2007). However, each technique has its own limitation. Mechanical polishing technique easily induces artifact by mechanical force, especially on advance technology node. FIB can eliminate mechanically damaged artifact, but have the limitation on cross-sectional view area. Another potential technique will be plasma FIB, it used very high milling current and fast milling speed (Hrnčíř et al., 2013). However, it comes with a very high cost and having the contamination issue. The contamination issue greatly affects the low kV Scanning Electron Microscopy (SEM) imaging quality. In recent semiconductor industry FA, low kV SEM imaging is preferable, because high kV imaging will introduce delamination artifacts especially on organic material from packaged sample. In this paper, Fast Laser Deprocessing Techniques (FLDT) application is further enhanced on large area cross-sectional FA with fast cycle time and low-cost equipment. This is to prevent from mechanical damage. In short, the proposed FLDT is a cost-effective and quick way to deprocess a sample for defect identification in cross-sectional FA.

FEI Helios NanoLab 400S FIB-SEM

The FEI Helios NanoLab400S FIB-SEM is one of the world's most advanced DualBeamTM focused ion beam (FIB) platforms for transmission electron microscopy (TEM) sample preparation, scanning electron microscopy (SEM) imaging and analysis in semiconductor failure analysis, process development and process control. The FEI Helios NanoLab400S FIB-SEM combines an ElstarTM electron column for high-resolution and high-contrast imaging with a high-performance SidewinderM ion column for fast and precise cross sectioning. The FEI Helios NanoLab M 400S is optimised for high throughput high-resolution S/TEM sample preparation, SEM imaging and energy dispersive X-ray analysis. Its exclusive FlipStageTM and in situ STEM detector can flip from sample preparation to STEM imaging in seconds without breaking vacuum or exposing the sample to the environment. Platinum gas chemistry is the preferred metal deposition when a high deposition rate and precision of the deposition are required. Carbon deposition can be chosen as well. The system additionally allows for spatially resolved compositional analysis using the attached EDAX Genesis XM 4i X-ray microanalysis system.

Influence of Focused Electron Beam on Electrical Characterization of Advanced Mosfets

The focused electron beam based inspection instruments such as Scanning Electron Microscope (SEM) have become widespread in the semiconductor manufacturing and failure analysis of scaled devices. Also, nano-probing systems with SEM guidance have become important in the failure analysis area to evaluate the localized device in the actual LSI [1]. However, electron beam leads to device degradation [2] and its damage are increasing with the scaling. As CMOS scaling is going to be sub-10nm regime [3], electron beam damages are becoming critical issue in performing electrical characterization at the contact level in integrated devices using nano-probe technique. To avoid the electron damage, the acceleration voltage should be lower. However, the lower acceleration voltage of electron beam leads to lower resolution of image created by SEM guidance.In this work, we evaluated NMOS FinFET in SRAM cells manufactured in a 10nm CMOS process with Atomic Force Microscopy (AFM) based nano-probing system. AFM based nano-probing system has no electron beam damage because it uses topography image created by AFM instead of SEM for guidance at contact level [4]. After deprocessing the samples to the contact level, we irradiated electron beams to samples to investigate a dependency of the device characteristics on electron beam acceleration voltage. Compared to a non-exposed reference transistor, the exposure of electron beam on the target transistor lead to significant changes on device characteristics such as saturation current (IDS), sub-threshold voltage (VTH) and sub-threshold swing (S). This might be due to trapped charges in the gate oxide and interface state [5]. Our studies show that it is critical to avoid electron beam exposure before electrical device characterizations are carried out at the contact level using nano-probe system since electron beam induced device parameter changes are not negligible in the failure analysis of sub-10nm devices.

ISTFA 2014 Wrap-Up

Abstract The 40th International Symposium for Testing and Failure Analysis (ISTFA 2014) was held November 8 to 14, 2014, at the George R. Brown Convention Center in Houston, Texas. “Exploring the Many Facets of Failure Analysis,” the theme of ISTFA 2014, emphasized the diverse nature of semiconductor failure analysis in the 21st century. The technical sessions, keynotes, and tutorials at ISTFA 2014 covered a wide range of topics from fault isolation and sample prep to extreme environment failures and the birth of the digital signal processor.

Failure Analysis: Why Mistakes Are Made and How to Avoid Making One

Abstract The tools of the trade in semiconductor failure analysis have advanced rapidly over the past few decades, bringing major improvements in imaging, deprocessing, and materials analysis. In contrast to the progress made in physical FA, little attention has been given to the failure analysis process itself. This article shows through case studies how simple oversights and misunderstandings can lead to costly mistakes. It also defines basic FA concepts and presents a failure analysis sequence, describing each step along with common pitfalls and best practices.

SEM-based nanoprobing on 32 and 28 nm CMOS devices challenges for semiconductor failure analysis

This paper presents an effective device-level failure analysis (FA) method which uses a high-resolution low-kV Scanning Electron Microscope (SEM) in combination with an integrated state-of-the-art nanomanipulator to locate and characterize single defects in failing CMOS devices. The presented case studies utilize several FA-techniques in combination with SEM-based nanoprobing for nanometer node technologies and demonstrate how these methods are used to investigate the root cause of IC device failures. The methodology represents a highly-efficient physical failure analysis flow for 28nm and larger technology nodes.

Optimization of High Current Xenon Plasma Ion Beams for Applications in Semiconductor Failure Analysis and Development

Optimization of High Current Xenon Plasma Ion Beams for Applications in Semiconductor Failure Analysis and Development