Failure Bitmaps Research Articles

A Local Parallel Search Approach for Memory Failure Pattern Identification

Due to more aggressive design rules adopted by memories than logic circuits, memories have been considered as the major technology driver of advanced logic circuits, so far as CMOS process technology is concerned. Memory failure pattern identification therefore is important, and is traditionally considered a key task that can help improve the efficiency of memory diagnosis and failure analysis. Critical failure patterns (that are the yield killers), however, may change in different memory designs and process technologies. It is difficult to identify critical failure patterns from high-volume memory failure bitmaps if they are not predefined. To solve this problem, we propose a local parallel search algorithm for efficient memory failure pattern identification. In addition, the proposed system integrates the defect-spectrum-based and coordinate-distance-based methods to identify critical memory failure patterns from a large amount of memory failure bitmaps automatically, even if they are not defined in advance. In our experiment for 132,488 4-MB memory failure bitmaps, the proposed system can automatically identify six critical yet undefined failure patterns in minutes, in addition to all known patterns. In comparison, the state-of-the-art commercial tools need manual inspection of the memory failure bitmaps to identify the same failure patterns.

A Regularized Singular Value Decomposition-Based Approach for Failure Pattern Classification on Fail Bit Map in a DRAM Wafer

In semiconductor manufacturing processes, monitoring the quality of wafers is one of the most important steps to quickly detect process faults and significantly reduce yield loss. Fail bit maps (FBMs) represent the failed cell count during wafer functional tests and have been popularly used as one of the diagnosis tools in semiconductor manufacturing for process monitoring, root cause analysis, and yield improvements. However, the visual inspection process is costly and time-consuming. Therefore, this paper proposes an automated classification procedure for failure patterns on FBMs in dynamic random access memory (DRAM) wafers. The novel matrix factorization approach, called regularized singular value decomposition, is proposed to decompose binarized FBMs into several eigen-images to extract features that can provide the characteristics of the failure patterns on FBMs. By using the extracted features, k-nearest neighbor classifier is employed to classify feature patterns on FBMs into single bit failure maps and non-single bit failure ones. The proposed procedure is tested on real-life DRAM wafer data set provided by a semiconductor manufacturing industry, and promising results have been obtained for the automatic classification of single bit and non-single bit failure maps.

A Large-Scale, Flip-Flop RAM Imitating a Logic LSI for Fast Development of Process Technology

We propose a new large-scale logic test element group (TEG), called a flip-flop RAM (FF-RAM), to improve the total process quality before and during initial mass production. It is designed to be as convenient as an SRAM for measurement and to imitate a logic LSI. We implemented a 10 Mgates FF-RAM using our 65-nm CMOS process. The FF-RAM enables us to make fail-bit maps (FBM) of logic cells because of its cell array structure as an SRAM. An FF-RAM has an additional structure to detect the open and short failure of upper metal layers. The test results show that it can detect failure locations and layers effortlessly using FBMs. We measured and analyzed it for both the cell arrays and the upper metal layers. Their results provided many important clues to improve our processes. We also measured the neutron-induced soft error rate (SER) of FF-RAM, which is becoming a serious problem as transistors become smaller. We compared the results of the neutron-induced soft error rate to those of previous generations: 180nm, 130nm, and 90nm. Because of this TEG, we can considerably shorten the development period for advanced CMOS technology.

Defective Contacts in DRAMS: From Electrical to Physical Failure Analysis

Abstract This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.