Fabrication Of Field-effect Transistors Research Articles

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

Quasi-Van der Waals Epitaxial Growth of γ'-GaSe Nanometer-Thick Films on GaAs(111)B Substrates.

GaSe is an important member of the post-transition-metal chalcogenide family and is an emerging two-dimensional (2D) semiconductor material. Because it is a van der Waals material, it can be fabricated into atomic-scale ultrathin films, making it suitable for the preparation of compact, heterostructure devices. In addition, GaSe possesses unusual optical and electronic properties, such as a shift from an indirect-bandgap single-layer film to a direct-bandgap bulk material, rare intrinsic p-type conduction, and nonlinear optical behaviors. These properties make GaSe an appealing candidate for the fabrication of field-effect transistors, photodetectors, and photovoltaics. However, the wafer-scale production of pure GaSe single-crystal thin films remains challenging. This study develops an approach for the direct growth of nanometer-thick GaSe films on GaAs substrates by using molecular beam epitaxy. It yields smooth thin GaSe films with a rare γ'-polymorph. We analyze the formation mechanism of γ'-GaSe using density-functional theory and speculate that it is stabilized by Ga vacancies since the formation enthalpy of γ'-GaSe tends to become lower than that of other polymorphs when the Ga vacancy concentration increases. Finally, we investigate the growth conditions of GaSe, providing valuable insights for exploring 2D/three-dimensional (3D) quasi-van der Waals epitaxial growth.

Effect of rapid thermal annealing on DC performance of Mg0.30Zn0.70O/Cd0.15Zn0.85O MOSHFET

This study focuses on a cost-effective method for fabrication of a metal oxide semiconductor-heterostructure field effect transistor (MOSHFET) based on MgZnO/CdZnO (MCO) using dual ion beam sputtering (DIBS), in contrast to the more expensive epitaxial growth system. The MOSHFETs developed in this research exhibit notable characteristics, such as a substantial two-dimensional electron gas (2DEG) transconductance (∼2.6 mS), a high ION/IOFF response ratio in the order of 108, and minimal gate leakage current. Furthermore, we explore the impact of rapid thermal annealing (RTA) on the drain current at various temperatures (600 °C and 800 °C). The results indicate a fourfold improvement in drain current compared to unannealed conditions, primarily attributed to reduced contact resistance and no degradation in term of MgZnO/CdZnO structure. Additionally, an analysis of post-RTA treatment under a nitrogen (N2) atmosphere on gate leakage current is presented. The investigation spans temperatures ranging from 400 °C to 800 °C, revealing that above 600 °C (gate leakage at 400 °C–600 °C is around ∼10−9 A), gate leakage in HFET is augmented by one order of magnitude (∼10−8 A) due to a phase change in the dielectric. These findings underscore the feasibility of DIBS-grown MCO MOSHFETs as an economical solution for the mass production of switching devices and sensors.

Realization of single MoTe2 crystal in-plane TFET by laser-induced doping technique

Significant recent progress has been achieved in the fabrication of tunnel field-effect transistors (TFETs) utilizing transition metal dichalcogenides (TMDCs) materials, particularly focusing on out-of-plane heterojunction structures. Due to the inherent limitations of doping technology for TMDCs, there have been limited investigations into the development of in-plane TFETs. In this study, we present the realization of an in-plane TFET based on a single crystal of multilayer MoTe2, utilizing a regioselective doping technique through laser irradiation. By constructing a p+/i/n++ homojunction structure, a band-to-band tunneling dominated performance with a minimum subthreshold swing value of 75 mV/dec and an on/off ratio of 105 was obtained at a low temperature. Furthermore, the “OFF” and “ON” state currents of the TFET operation were smaller than the gated diode operation in this structure, which is consistent with the tunneling mechanism.

Comprehensive Study and Design of Graphene Transistor.

Graphene, renowned for its exceptional electrical, optical, and mechanical properties, takes center stage in the realm of next-generation electronics. In this paper, we provide a thorough investigation into the comprehensive fabrication process of graphene field-effect transistors. Recognizing the pivotal role graphene quality plays in determining device performance, we explore many techniques and metrological methods to assess and ensure the superior quality of graphene layers. In addition, we delve into the intricate nuances of doping graphene and examine its effects on electronic properties. We uncover the transformative impact these dopants have on the charge carrier concentration, bandgap, and overall device performance. By amalgamating these critical facets of graphene field-effect transistors fabrication and analysis, this study offers a holistic understanding for researchers and engineers aiming to optimize the performance of graphene-based electronic devices.

Removal of conjugated polymer on carbon nanotube array by dry process

With the progress in the purity and alignment of semiconductor carbon nanotubes (CNTs), how to efficiently remove the conjugated polymers twining round CNTs has become an important and urgent matter for the further development of CNT electronics. The removal of conjugated polymers (CPs) by wet cleaning will inevitably lead to the destruction of the morphology of aligned CNT array films, which will cause the monolayered CNTs to form agglomeration or stacking. Therefore, it is necessary to develop a dry method to remove CPs on the aligned CNT films. In this work, we studied the thermal decomposition characteristics of CNTs and CPs in detail, and found that the ratio of the oxidative decomposition rate of CNTs and CPs could reach up to 35.7 in the oxygen environment at 450 °C. The transmission electron microscopes (TEMs) show that such a dry treatment process can effectively remove the polymer on CNTs without affecting the morphology of CNT arrays. The Raman spectrum show that ratio of G/D of the annealed sample is as high as 41.8, which indicates that the CNTs are not detectable damaged during the annealed process. The fabricated field-effect transistors (FETs) with a length of 2 μm exhibit a current on/off ratio higher than 104 and a current density higher than 660 μA/μm, which further justifies that the CNT arrays treated by the dry method exhibit high quality.

Effect of Thickness and Thermal Treatment on the Electrical Performance of 2D MoS2 Monolayer and Multilayer Field-Effect Transistors

We deposited high-quality molybdenum disulfide (MoS2) monolayer and multilayer crystals on SiO2/Si substrates, by means of a chemical vapor deposition (CVD) process at atmospheric pressure. Notably, NaCl salt was used as component of the precursors to assist the growth of MoS2 crystals, which were intended for use as the active channel layer in the fabrication of field-effect transistors (FETs). The resulting MoS2 crystals from this CVD process were analyzed by optical, scanning electron, and atomic force microscopies, and by Raman and photoluminescence spectroscopies. The optical images and the micrographs obtained by SEM revealed the formation of dispersed MoS2 crystals with a triangular shape all over the SiO2 surface. The thickness of the MoS2 crystals, analyzed by atomic force microscopy, showed minimum values of around 0.7 nm, confirming the formation of monolayers. Additionally, multilayers with larger thickness were also identified. The Raman and photoluminescence spectra of the MoS2 crystals corroborated the formation of single and multiple layers. The fabrication of the FET back-SiO2 -gate configuration was made by depositing patterned source and drain Ti contacts on the dispersed MoS2 crystals to achieve the Ti/MoS2/SiO2/Si layer stacks. MoS2-based FETs with one and three layers were assembled and their electrical response analyzed by I–V output and transfer curves showing the typical characteristics of an n-type semiconductor channel operating in depletion mode. The electrical performance parameters of the devices, such as mobility and threshold voltage, were also determined from this analysis. Finally, to enhance their electrical response, the MoS2-based devices were thermally annealed at 200 °C for 30 min in Ar atmosphere. The increase in the mobility of the device was 176% compared to the device before the treatment.

Analytical modelling and reliability analysis of charge plasma-assisted Mg2Si/Si heterojunction doping less DGTFET for low-power switching applications

Fabrication of tunnel field effect transistor (TFET) confronts various challenges, one of which is random dopant fluctuation (RDF), which diminishes the benefits associated with low subthreshold swing (SS) and high ION/IOFF ratio. By conducting physics-based 2D analytical modelling, this paper proposes a magnesium silicide/silicon (Mg2Si/Si) heterojunction-based doping less double gate tunnel field effect transistor (HB-DL-DGTFET). This work utilizes the concept of charge plasma to tackle the issues of RDF. The analytical analysis in this study is based upon the determination of the center-channel potential by solving 2D Poisson’s equation, considering appropriate boundary conditions. Here, surface potential, electric field, energy bands, drain current and threshold voltage are extracted mathematically. In addition to the aforementioned parameters, several other analog performance parameters like transconductance, drain conductance, device efficiency, intrinsic gain, output resistance and channel resistance have also been studied in this context. The analytical findings have been duly validated using the ATLAS TCAD device simulator. Furthermore, this work focuses on exploring proposed device reliability through an investigation of, the influence of interface trap charges (ITC), present at the Si/SiO2 interface. The study analyses ITC's impact on analog performance and the obtained results are compared with that of conventional doping less DGTFET (C-DL-DGTFET). The simulation results reveal that HB-DL-DGTFET exhibits greater immunity against ITC. Thus, validating the potential of HB-DL-DGTFET as a superior candidate for low-power switching applications.

Space-Confined Synthesis of Monolayer Graphdiyne in MXene Interlayer.

Graphdiyne (GDY) is an artificial carbon allotrope that is conceptually similar to graphene but composed of sp- and sp2 -hybridized carbon atoms. Monolayer GDY (ML-GDY) is predicted to be an ideal 2D semiconductor material with a wide range of applications. However, its synthesis has posed a significant challenge, leading to difficulties in experimentally validating theoretical properties. Here, it is reported that in situ acetylenic homocoupling of hexaethynylbenzene within the sub-nanometer interlayer space of MXene can effectively prevent out-of-plane growth or vertical stacking of the material, resulting in ML-GDY with in-plane periodicity. The subsequent exfoliation process successfully yields free-standing GDY monolayers with micrometer-scale lateral dimensions. The fabrication of field-effect transistor on free-standing ML-GDY makes the first measurement of its electronic properties possible. The measured electrical conductivity (5.1 × 103 S m-1 ) and carrier mobility (231.4 cm2 V-1 s-1 ) at room temperature are remarkably higher than those of the previously reported multilayer GDY materials. The space-confined synthesis using layered crystals as templates provides a new strategy for preparing 2D materials with precisely controlled layer numbers and long-range structural order.

Design, fabrication and measurement of metal-semiconductor field effect transistor based on zinc oxide material

The paper mainly focuses on the design, fabrication and measurement on Zinc Oxide (ZnO)-based Metal-Semiconductor Field Effect Transistor. The research problem in this study is difficulty on observing the electronic properties of ZnO materials to fabricate the high performance transistor design with non-toxic semiconductor materials. Even though the wide band gap materials of Group III and V possess high performance properties for fabricating the power electronics devices, the harmful impacts could not be reduced. The research solution for the problem statement in this study is emphasized on the non-toxic materials of Group II and VI-based high performance power electronics devices fabrication. The experimental studies of the device fabrication were conducted by Pulse Laser Deposition (PLD) process in standard laboratory. The step-by-step procedures for MSFET device fabrication were discussed and the confirmation of developed device fabrication was completed. The approaches on all measurement were completed based on band diagram condition, quantum interference on metal-semiconductor materials, and current-voltage characteristics. The step by step measurement for fabricated device for the proposed structure could be confirmed by standard measurement techniques. The proposed design has been validated for the utilization of high performance applications. The physical properties and physical characteristics for measurement results were confirmed by the theoretical analyses. The numerical analyses have been completed with the help of MATLAB. All results have been proved by recent research works.

The Role of Carbon in Metal-Organic Chemical Vapor Deposition-Grown MoS2 Films.

Acquiring homogeneous and reproducible wafer-scale transition metal dichalcogenide (TMDC) films is crucial for modern electronics. Metal-organic chemical vapor deposition (MOCVD) offers a promising approach for scalable production and large-area integration. However, during MOCVD synthesis, extraneous carbon incorporation due to organosulfur precursor pyrolysis is a persistent concern, and the role of unintentional carbon incorporation remains elusive. Here, we report the large-scale synthesis of molybdenum disulfide (MoS2) thin films, accompanied by the formation of amorphous carbon layers. Using Raman, photoluminescence (PL) spectroscopy, and transmission electron microscopy (TEM), we confirm how polycrystalline MoS2 combines with extraneous amorphous carbon layers. Furthermore, by fabricating field-effect transistors (FETs) using the carbon-incorporated MoS2 films, we find that traditional n-type MoS2 can transform into p-type semiconductors owing to the incorporation of carbon, a rare occurrence among TMDC materials. This unexpected behavior expands our understanding of TMDC properties and opens up new avenues for exploring novel device applications.

Biodegradable albumen dielectrics for high-mobility MoS2 phototransistors

This work demonstrates the fabrication and characterization of single-layer MoS2 field-effect transistors using biodegradable albumen (chicken eggwhite) as gate dielectric. By introducing albumen as an insulator for MoS2 transistors high carrier mobilities (up to ~90 cm2 V−1 s−1) are observed, which is remarkably superior to that obtained with commonly used SiO2 dielectric which we attribute to ionic gating due to the formation of an electric double layer in the albumen MoS2 interface. In addition, the investigated devices are characterized upon illumination, observing responsivities of 4.5 AW−1 (operated in photogating regime) and rise times as low as 52 ms (operated in photoconductivity regime). The presented study reveals the combination of albumen with van der Waals materials for prospective biodegradable and biocompatible optoelectronic device applications. Furthermore, the demonstrated universal fabrication process can be easily adopted to fabricate albumen-based devices with any other van der Waals material.

Amplifying the dielectric constant of shellac by incorporating natural clays for organic field effect transistors (OFETs).

We demonstrate in this work the practical use of uniform mixtures of a bioresin shellac and four natural clays, i.e. montmorillonite, sepiolite, halloysite and vermiculate as dielectrics in organic field effect transistors (OFETs). We present a thorough characterization of their processability and film forming characteristic, surface characterization, elaborate dielectric investigation and the fabrication of field effect transistors with two classic organic semiconductors, i.e. pentacene and fullerene C60. We show that low operating voltage of approximately 4 V is possible for all the OFETs using several combinations of clays and shellac. The capacitance measurements show an improvement of the dielectric constant of shellac by a factor of 2, to values in excess of 7 in the uniform mixtures of sepiolite and montmorillonite with this bioresin.

Optimization of Layer Transfer and Photolithography for Device Integration of 2D-TMDC

Extensive research into two-dimensional transition metal dichalcogenides (2D-TMDCs) over the past decade has paved the way for the development of (opto)electronic devices with enhanced performance and novel capabilities. To realize devices based on 2D-TMDC layers, compatible and optimized technologies such as layer transfer and photolithography are required. Challenges arise due to the ultrathin, surface-only nature of 2D layers with weak van der Waals adhesion to their substrate. This might potentially compromise their integrity during transfer and photolithography processes, in which prolonged exposure at usually high temperature to reactive chemicals and strong solvents are conventionally used. In this paper, we show that employing a dry-transfer technique based on thermal release tape (TRT) as an alternative to wet processes based on KOH solution better preserves layer quality. In the succeeding device fabrication process, an optimized photolithography as a cost-effective and widely available method for device patterning is utilized. The introduced photolithography protocol presents a near-perfect yield and reproducibility. To validate our optimized techniques, we fabricated field-effect transistors (FETs) using 2D-MoS2 layers from metal–organic chemical vapor deposition (MOCVD), wet- and dry-transferred onto SiO2/Si substrates. Our findings mark a significant stride towards the efficient and industry-compatible utilization of 2D van der Waals materials in device fabrication.

Biotemplated precise assembly approach toward ultra-scaled high-performance electronics.

Structural DNA nanotechnology can be programmed into complex designer structures with molecular precision for directing a wide range of inorganic and biological materials. However, the use of DNA-templated approaches for the fabrication and performance requirements of ultra-scaled semiconductor electronics is limited by its assembly disorder and destructive interface composition. In this protocol, using carbon nanotubes (CNTs) as model semiconductors, we provide a stepwise process to build ultra-scaled, high-performance field-effect transistors (FETs) from micron-scale three-dimensional DNA templates. We apply the approach to assemble CNT arrays with uniform pitches scaled between 24.1 and 10.4 nm with yields of more than 95%, which exceeds the resolution limits of conventional lithography. To achieve highly clean CNT interfaces, we detail a rinsing-after-fixing step to remove residual DNA template and salt contaminations present around the contact and the channel regions, without modifying the alignment of the CNT arrays. The DNA-templated CNT FETs display both high on-state current (4-15 μA per CNT) and small subthreshold swing (60-100 mV per decade), which are superior to previous examples of biotemplated electronics and match the performance metrics of high-performance, silicon-based electronics. The scalable assembly of defect-free three-dimensional DNA templates requires 1 week and the CNT arrays can be synthesized within half a day. The interface engineering requires 1-2 d, while the fabrication of high-performance FET and logic gate circuits requires 2-4 d. The structural and performance characterizations of molecular-precise DNA self-assembly and high-performance electronics requires 1-2 d. The protocol is suited for users with expertise in DNA nanotechnology and semiconductor electronics.

Effects of Processing-Induced Contamination on Organic Electronic Devices.

Organic semiconductors are a family of pi-conjugated compounds used in many applications, such as displays, bioelectronics, and thermoelectrics. However, their susceptibility to processing-induced contamination is not well understood. Here, it is shown that many organic electronic devices reported so far may have been unintentionally contaminated, thus affecting their performance, water uptake, and thin film properties. Nuclear magnetic resonance spectroscopy is used to detect and quantify contaminants originating from the glovebox atmosphere and common laboratory consumables used during device fabrication. Importantly, this in-depth understanding of the sources of contamination allows the establishment of clean fabrication protocols, and the fabrication of organic field effect transistors (OFETs) with improved performance and stability. This study highlights the role of unintentional contaminants in organic electronic devices, and demonstrates that certain stringent processing conditions need to be met to avoid scientific misinterpretation, ensure device reproducibility, and facilitate performance stability. The experimental procedures and conditions used herein are typical of those used by many groups in the field of solution-processed organic semiconductors. Therefore, the insights gained into the effects of contamination are likely to be broadly applicable to studies, not just of OFETs, but also of other devices based on these materials.

Fabrication of a Field-Effect Transistor Based on 2D Novel Ternary Chalcogenide PdPS.

Two-dimensional (2D) palladium phosphide sulfide (PdPS) has garnered significant attention, owing to its exotic physical properties originating from the distinct Cairo pentagonal tiling topology. Nevertheless, the properties of PdPS remain unexplored, especially for electronic devices. In this study, we introduce the thickness-dependent electrical characteristics of PdPS flakes into fabricated field-effect transistors (FETs). The broad thickness variation of the PdPS flakes, ranging from 0.7-306 nm, is prepared by mechanical exfoliation, utilizing large bulk crystals synthesized via chemical vapor transport. We evaluate this variation and confirm a high electron mobility of 14.4 cm2 V-1 s-1 and Ion/Ioff > 107. Furthermore, the 6.8 nm-thick PdPS FET demonstrates a negligible Schottky barrier height at the gold electrode contact, as evidenced by the measurement of the temperature-dependent transfer characteristics. Consequently, we adjusted the Fowler-Nordheim tunneling mechanism to elucidate the charge-transport mechanism, revealing a modulated mobility variation from 14.4 to 41.2 cm2 V-1 s-1 with an increase in the drain voltage from 1 to 5 V. The present findings can broaden the understanding of the unique properties of PdPS, highlighting its potential as a 2D ternary chalcogenide in future electronic device applications.

Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe2) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe2 is suitable for an application to CMOS inverter.One of the significant challenges is to develop a top gate and top contact FET structure with WSe2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WOx, which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device.Figures 1 shows the self-aligned fabrication process of p-type WSe2 FET. 20 nm-thick SiO2 was formed by dry oxidation of p+-Si substrate. The mechanically exfoliated multi-layer WSe2 was transferred by PDMS stamp. Next, 15 nm-thick Al2O3 was prepared by ALD at 200 oC with H2O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al2O3. Ni metal was patterned for gate electrode with conventional lithography process. After that, A2O3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WOx used as source/drain contact at surface of WSe2. Second layer of Al2O3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N2 : H2 = 97 % : 3 %) annealing was performed at 200 oC for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C).Figures 2 shows the Id–Vg characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative Id–Vg characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 106 ~ 107 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep.This study opens up interesting directions for the research and development of TMDC-based devices.AcknowledgmentsThis study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award.

Fabrication of flexible organic field effect transistors with high carrier mobility via sheath gas-assisted direct writing Poly(3-hexylthiophene) solution

Fabrication of flexible organic field effect transistors with high carrier mobility via sheath gas-assisted direct writing Poly(3-hexylthiophene) solution

Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs

This paper proposes and demonstrates single-crystal Germanium (Ge) growth by elevated-laser-liquid-phase-epitaxy (ELLPE) and the fabrication of Ge Fin field-effect transistors (FinFETs) for the monolithic three-dimensional integrated circuits (monolithic 3D ICs). This technique permitted the fabrication of single-crystalline (100) Ge film and FinFETs without random grain boundaries. In comparison with the poly-Ge FinFETs, the ELLPE Ge FinFETs exhibit superior performance and uniformity. Moreover, the ANSYS simulated maximum temperature of bottom circuits during the ELLPE technique does not exceed 400°C, therefore allowing monolithic 3D integration of ICs.