Extrinsic Information Transfer Chart Technique Research Articles

3D EXIT Charts for Analyzing the 5G 3GPP New Radio LDPC Decoder

Low Density Parity Check (LDPC) codes have been selected to provide channel coding for data in the next generation of wireless communication standard referred to in practice as the 3GPP New Radio (NR). In contrast to the LDPC codes adopted in previous standards, the NR LDPC code can be considered to be a concatenation of a core LDPC code and a Low Density Generator Matrix (LDGM) code. This particular feature has the advantage of offering flexible coding rate, but it prevents the application of conventional extrinsic information transfer (EXIT) chart analysis. This article characterizes this problem and addresses it using a novel reinterpretation of the NR LDPC factor graph. Based on this factor graph, a novel 3D EXIT chart technique is conceived for our three-stage scheme, which facilitates the visual characterisation of the NR LDPC decoder's iterative decoding convergence process for the first time. The proposed EXIT chart analysis accurately visualizes the mutual information exchange amongst the components of the NR LDPC decoder, which was not facilitated by the conventional 2D EXIT chart. We demonstrate the power of this technique by using it to design a novel iterative decoding activation order for the NR LDPC decoder, which reduces the decoding complexity by approximately 17% compared to a conventional flooding decoder. This is achieved without degrading its error correction capability. We conclude by discussing several other opportunities for exploiting the proposed 3D EXIT chart technique to improve the design of concatenated LDPC and LDGM codes.

Conceiving Extrinsic Information Transfer Charts for Stochastic Low-Density Parity-Check Decoders

Stochastic low-density parity-check decoders (SLDPCs) have found favor recently both for correcting transmission errors as well as for improving the hardware efficiency. The main drawback of these decoders is that they require hundreds of time periods to decode each frame, but their chip area is smaller than that of their fixed-point counterparts, so they can achieve higher hardware efficiency and may consume less energy. In this paper, we propose a novel extrinsic information transfer chart technique for characterizing the iterative decoding convergence of all the sequences involved in the SLDPC. We have conceived a new model, which takes into consideration not only the sequences exchanged between the decoders but also the sequences generated inside the variable-node decoder (those which are stored in the edge memories). In this way, the model is able to predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by own decoder simulations. The proposed technique offers new insights into the operation of SLDPCs, which will facilitate improved designs for the research community.

Extrinsic Information Transfer Charts for Characterizing the Iterative Decoding Convergence of Fully Parallel Turbo Decoders

Fully parallel turbo decoders (FPTDs) have been shown to offer a more-than-sixfold processing throughput and latency improvement over the conventional logarithmic Bahl–Cocke–Jelinek–Raviv (Log-BCJR) turbo decoders. Rather than requiring hundreds or even thousands of time periods to decode each frame, such as the conventional Log-BCJR turbo decoders, the FPTD completes each decoding iteration using only one or two time periods, although up to six times as many decoding iterations are required to achieve the same error correction performance. Until now, it has not been possible to explain this increased iteration requirement using an extrinsic information transfer (EXIT) chart analysis, since the two component decoders are not alternately operated in the FPTD. Hence, in this paper, we propose a novel EXIT chart technique for characterizing the iterative exchange of not only extrinsic logarithmic likelihood ratios in the FPTD, but also the iterative exchange of extrinsic state metrics. In this way, the proposed technique can accurately predict the number of decoding iterations required for achieving iterative decoding convergence, as confirmed by the Monte Carlo simulation. The proposed technique offers new insights into the operation of FPTDs, which will facilitate improved designs in the future, in the same way as the conventional EXIT charts have enhanced the design and understanding of the conventional Log-BCJR turbo decoders.

EXIT chart aided design of periodically punctured turbo codes

Extrinsic information transfer (EXIT) charts have proved to be an effective tool for studying the convergence behaviour of iterative decoders. However, classical EXIT chart analysis fails to assess the performance of turbo codes in which the systematic bits are punctured periodically. A novel three-dimensional (3D) EXIT chart technique is proposed for accurately modelling the convergence behaviour of turbo codes that are punctured following a periodic pattern. Finally, the novel 3D EXIT chart technique is validated for a particular periodic turbo code, which is shown to outperform the equivalent randomly punctured code.

Bit-Interleaved Turbo Equalization Over Static Frequency-Selective Channels: Constellation Mapping Impact

The purpose is to assess the performance of bit-interleaved turbo equalization (TE) over static frequency-selective channels. The asymptotic performance is therefore first pointed out, emphasizing the fundamental role played by the constellation mapping. This specific feature is then further analyzed using the extrinsic information-transfer chart technique, leading to an efficient optimization tool. This finally enables showing that bit-interleaved TE can outperform its symbol-interleaved counterpart.