Extracted Contact Resistance Research Articles

A novel approach for extracting contact impedance of electrode/electrolyte interface by minimizing error between impulse response and system function

Electrochemical impedance spectroscopy (EIS) is widely used to analyze the electrode/electrolyte interface, but it has the disadvantage of long measurement time. Previous studies reduced this latency by utilizing specific waveforms such as square and dynamic signals. However, these methods can easily lose phase information due to the measurement noise and constrained sampling rate, which compromises the accuracy of impedance calculations. Here, we propose a novel approach to rapidly extract electrochemical properties at the electrode/electrolyte interface using only the magnitude information of measured signals. The proposed method obtains the contact impedance by minimizing the magnitude error between the theoretical system function and the measured impulse response, demonstrating greater resilience to the phase loss. When calculating the difference rate with conventional EIS, the extracted contact resistance and capacitance data exhibit a 10.34 % and 59.24 % improvement, respectively, compared to the previous approach that utilizes the Nyquist plot incorporating phase data.

High-performance monolayer MoS2 nanosheet GAA transistor

In this article, a 0.7 nm thick monolayer MoS2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high-κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μA μm−1 with a large on/off ratio of 6 × 108 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μm in monolayer MoS2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications.

Spreading Resistance Modeling for Contact Resistivity Extraction in Ohmic Multilayer Structures With Circular Electrodes

Contacts featuring multiple layers of materials in combination with metal electrodes enabled record-high power conversion efficiencies for solar cells in recent years. Minimizing the contact resistivity in these multilayer structures is critical to achieve a high device performance and rapid characterization methods are crucial for the experimental analysis of this aspect. However, commonly used test methods and the associated mathematical formulations to extract contact resistivity are not designed for samples with multiple layers. In this work, we analyze formulations describing the resistance measured in ohmic multilayer test structures, which are used to fit and extract an unknown contact resistivity. We focus on a contacting scheme with circular electrodes, commonly named after Cox and Strack (CS), and analyze a material configuration consisting of a thick Si substrate fully coated with a thin conductive layer (CL). We demonstrate the applicability and accuracy of various spreading resistance models (SRMs) from the literature to calculate the measured resistance and compare the results with those obtained by the finite element method (FEM). Moreover, we present a new SRM with a closed-form expression for the measured resistance, which is computationally more efficient than the existing SRMs. Last, we demonstrate the applicability of this model in experiments with ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> )c-Si/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${i}$ </tex-math></inline-formula> )a-Si:H/( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> )a-Si:H/indium tin oxide (ITO) test structures.

A novel method to extract contact resistivity for thermoelectric semiconductor.

Contact electrical resistance is a critical issue to be addressed in thermoelectric modules. A commercial instrument in thermoelectricity is demonstrated for the first time to extract the contact resistivity of thermoelectric legs by use of the three options of the probe distance. The specimen comprises two legs of bismuth telluride that are connected with reflow soldering. The probe distances are calibrated with a homogeneous sample of constantan. The linear fittings between the electrical resistance and the probe gap are employed in the calibration and in deriving the contact resistivity. The contact resistivity of n-type Bi2Te3 and p-type Bi2Te3 with nickel plating to the Sn64Bi35Ag1 solder is determined to be 17.4 µΩ cm2 and 9.8 µΩ cm2 at ambient temperature, respectively. The contact resistivities at two other temperatures are extracted as well so that the contact resistivity as a function of temperature would be available from the proposed method.

Contact resistance assessment and high-frequency performance projection of black phosphorus field-effect transistor technologies

In this work, an evaluation of the contact quality of black phosphorus field-effect transistors from different technologies previously reported is performed by means of an efficient and reliable contact resistance extraction methodology based on individual device practical characteristics. A good agreement is achieved between the extracted values with the Y-function method used here and reference values obtained with other methods considering internal values as well as with more expensive methods involving fabricated test structures. The method enables a direct evaluation of different steps in the same technology and it embraces the temperature dependence of the contact characteristics. Channel phenomena have no impact on the extracted contact resistance values. High-frequency performance projections are obtained for fabricated devices based on the extracted contact resistance.

Contact resistance extraction of graphene FET technologies based on individual device characterization

Straightforward contact resistance extraction methods based on electrical device characteristics are described and applied here to graphene field-effect transistors from different technologies. The methods are an educated adaptation of extraction procedures originally developed for conventional transistors by exploiting the drift–diffusion-like transport in graphene devices under certain bias conditions. In contrast to other available approaches for contact resistance extraction of graphene transistors, the practical methods used here do not require either the fabrication of dedicated test structures or internal device phenomena characterization. The methodologies are evaluated with simulation-based data and applied to fabricated devices. The extracted values are close to the ones obtained with other more intricate methodologies. Bias-dependent contact and channel resistances studies, bias-dependent high-frequency performance studies and contact engineering studies are enhanced and evaluated by the extracted contact resistance values.

Au-free recessed Ohmic contacts to AlGaN/GaN high electron mobility transistor: Study of etch chemistry and metal scheme

The authors study the effect of etch chemistry and metallization scheme on recessed Au-free Ohmic contacts to AlGaN/GaN heterostructures on silicon. The effect of variation in the recess etch chemistry on the uniformity of Ohmic contact resistance has been studied using two different etch chemistries (BCl3/O2 and BCl3/Cl2). Experiments to determine the optimum recess etch depth for obtaining a low value of contact resistance have been carried out, and it is shown that near-complete etching of the AlGaN barrier layer before metallization leads to the lowest value of contact resistance. Furthermore, two metal schemes, namely, Ti/Al and Ti/Al/Ti/W, are investigated, and it is found that the Ti/W cap layer on Ti/Al leads to low contact resistance with a smooth contact surface morphology. The effect of maintaining unequal mesa and contact pad widths on the extracted values of contact resistance and sheet resistance using the linear transfer length method (LTLM) has been studied. This is important as LTLM structures are used as monitors for process control during various steps of fabrication. It is shown that the extracted contact resistance and sheet resistance values are reliable when the mesa width is equal to the contact pad width. Finally, a possible mechanism for carrier transport in the Ohmic contacts formed using this process has been discussed, based on temperature dependent electrical characterization, and the field emission mechanism is found to be the dominant mechanism of carrier transport. A low Ohmic contact resistance of 0.56 Ω mm, which is one of the lowest reported values for identical metal schemes, and good contact surface morphology has been obtained with moderate post-metal annealing conditions of 600°C.

Lateral transport in silicon solar cells

We investigate lateral charge carrier transport in crystalline silicon solar cells. Under typical operation illumination of high-efficiency solar cells, a significant population of electrons and holes exist in the silicon wafer, leading to a non-negligible sheet conductance for both carrier types. To investigate the contribution of these sheet conductances to lateral transport in solar cells, we develop a model that calculates the effective series resistance of two sheet resistances coupled via a contact resistance. In solar cells, the upper sheet resistance describes the highly conductive region like a diffusion or a transparent conductive oxide, whereas the lower sheet resistance describes the silicon absorber. We find that the coupling contact resistance needs to be low to benefit from the lateral current flow in the silicon absorber. We show experimentally for silicon heterojunction solar cells that the silicon absorber supports lateral minority charge carrier transport for well-passivated devices. Another finding is that there is no principle advantage for coupling of the two sheet resistances for rear-junction or front-junction solar cells, as the pn-junction (for front-junction solar cells) does not prevent coupling. We suggest that for n-type silicon heterojunction solar cells, the observed advantage of the rear-junction over the front-junction architecture is due to practically lower contact resistance and higher mobility of electrons vs holes. We also confirm experimentally the importance of a low contact resistivity between the highly conductive region and the silicon absorber for effective coupling and present an innovative technique to extract contact resistance from comparing Suns-VOC and current–voltage measurements.

Luminescence Image Analysis Using Finite-Element Models: Finished Solar Cell Analysis

A general computational routine which seeks cell parameters that best explain a set of luminescence imaging data is presented in this article. The routine combines Griddler, a finite-element simulator for solar cells, and tailored multivariate regression techniques. It is applied to a dataset of luminescence images from about 80 monocrystalline silicon Al back surface field solar cells with varying front metal grid contact resistance and recombination. The fitted cell parameters including contact resistance spatial distribution, saturation current densities of the wafer's passivated regions, and under the metal contacts lead to simulated I–V characteristics that are in agreement with experimental data. The extracted contact resistance also correlates well with transmission line method measurements. In a separate study of luminescence imaging data from a multicrystalline passivated emitter rear local contacted cell (PERC) cell, this analysis routine is also compared with an alternative high spatial resolution method, yielding comparable results.

Stability of radio-frequency graphene field-effect transistors in ambient

While many studies on radio-frequency (RF) graphene field-effect transistor (GFET) aimed to study its high performances, explorations of the long-term stability of RF GFETs in atmosphere may be required as well. In this paper, we investigated the stability of the RF GFETs stored in ambient for four years. Both the RF and direct current characteristics are measured and compared with the initial properties. Changes of current-gain cut-off frequency and field-effect mobility, reductions of maximum oscillation frequency, peak transconductance and gate capacitance are observed butthe extracted contact resistance remains unchanged. The permeation of water vapor and oxygen into the thin Al2O3 dielectric, the diffusion of Pd atoms from contact onto the graphene channel and the rougher Al2O3 surface may challenge the stability of RF GFETs. This work may pave the way for the fabrication of more stable RF GFETs, which further serve steady graphene-based RF circuits.

Wafer Scale Graphene Field Effect Transistors on Thin Thermal Oxide

In this study, we present the feasibility to fabricate back-gated graphene field-effect transistors (GFETs) on 10nm thermal SiO2 substrate. Here, we compare the mobility of graphene devices at different locations of the transferred CVD graphene. We observed that there is a n-type doping of the graphene devices with Dirac points within ±0.5V from an ideal value of 0V. The downscaling of the back-gate dielectric thickness reduces the operating voltage range, commonly required for low power electronics, and the devices are stable during operation in air under ambient conditions. The extracted contact resistance is comparable to the earlier reports found in literature and this provides a feasibility to fabricate low power futuristic graphene based nanoelectronics.

Analysis of charge injection and contact resistance as a function of electrode surface treatment in ambipolar polymer transistors

Ambipolar organic field-effect transistors (OFETs) have both of hole and electron enhancements in charge transport. The characteristics of conjugated diketopyrrolopyrrole ambipolar OFETs depend on the metal-contact surface treatment for charge injection. To investigate the charge-injection characteristics of ambipolar transistors, these devices are processed via various types of self-assembled monolayer treatments and annealing. We conclude that treatment by the self-assembled monolayer 1-decanethiol gives the best enhancement of electron charge injection at both 100 and 300 °C annealing temperature. In addition, the contact resistance is calculated by using two methods: One is the gated four-point probe (gFPP) method that gives the voltage drop between channels, and the other is the simultaneous contact resistance extraction method, which extracts the contact resistance from the general transfer curve. We confirm that the gFPP method and the simultaneous extraction method give similar contact resistance, which means that we can extract contact resistance from the general transfer curve without any special contact pattern. Based on these characteristics of ambipolar p- and n-type transistors, we fabricate inverter devices with only one active layer.

Extremely High-Frequency Flexible Graphene Thin-Film Transistors

We have achieved 140-nm channel length graphene thin-film transistors (TFTs) on flexible glass with a 95-GHz intrinsic cutoff frequency and greater than 30-GHz intrinsic power frequency after standard de-embedding. The flexible glass substrate offers subnanometer surface smoothness as well as high thermal conductivity, 1 W/ $\textrm {m}\,\cdot \, \textrm {K}$ , which can prevent thermomechanical failure, which is a limitation of plastic and rubber substrates. In addition, we developed a flexible 60-nm polyimide thin film as gate dielectric with low surface roughness less than 0.35 nm for optimal carrier transport and facilitate edge-injection contacts for low contact resistance. The maximum electron (hole) mobility is 4540 (1100) cm2/ $\textrm {V}\cdot \textrm {s}$ , and the extracted contact resistance in the electron (hole) branch is 1140 (720) $\Omega \cdot \mu \text{m}$ . The intrinsic cutoff frequency is 196% higher than our previous results on polymeric substrates. Importantly, the experimental saturation velocity of the graphene TFT is the highest for any flexible transistor on any material system reported so far.

A more reliable measurement method for metal/graphene contact resistance

The contact resistance of metal/graphene is becoming a major limiting factor for graphene devices. Among various kinds of contact resistance test methods, the transmission line model is the most common approach to extract contact resistance in graphene devices. However, experiments show that in some cases there exists large inaccuracy and instability using this method. In this study, we added a cross-bridge structure at the terminal of the transmission line as a supporting test. This modified transmission line measurement structure can easily compare not only the transmission line and Kelvin contact resistance, getting a more reliable value, but also the other contact-related parameters, such as specific contact resistivity, transfer length and the graphene sheet resistance under and outside contact metal at the same time. The new measurement test is very helpful in enabling us to study the contact property accurately. The specific contact resistivity in our experiment is in the range of 2.0 × 10−6 Ω · cm2 and 3.0 × 10−6 Ω · cm2 at room temperature. With the temperature decreasing from 290 K to 60 K, the transfer length fluctuates around 1.7 μm, and the specific contact resistivity reduces to less than 2.0 × 10−6 Ω · cm2.

NMOS contact resistivity reduction with implants into silicides

AbstractNMOS contact resistivity (ρc) for NiPtSi was reduced by up to 50% by implanting either Se or P into the silicide film, followed by thermally recrystallizing the silicide and activating the implanted species. The silicide module integration included use of plasma pre‐clean, a thin NiPt film, a low temperature soak anneal (RTP1), and millisecond laser anneals for post‐implant anneals (RTP2 and RTP3). Additionally, experiments with Se implants into TiSi2 achieved 60% reduction in ρc with exclusive use of laser anneals (for both RTP1 and RTP2). The test structures included van der Pauw, transmission line model (TLM) and diodes, all of which are testable after silicidation to extract of silicide phase and sheet resistance (Rs), silicide/SD external resistance (Rext), ρc, and junction breakdown (Vbj). In order to mimic realistic CMOS process flows, contact chain structures testable after metal‐1 were also used to obtain average resistance/contact and extract contact resistivity. The results in this work demonstrated adequate process window, while maintaining junction characteristics without degradation of Rs. Laser anneal steps were key enabler to achieve these results, and were designed to prevent dopant deactivation while minimizing diffusion of SD regions for USJ compatibility for sub‐20 nm CMOS nodes. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Practical Contact Resistance Measurement Method for Bulk Bi2Te3-Based Thermoelectric Devices

The impact of contact resistance on thermoelectric (TE) device performance grows more significant as devices are scaled down. To improve and understand the effects of contact resistance on bulk TE device performance, a reliable experimental measurement method is needed. There are many popular methods to extract contact resistance, but they are only well suited for measuring metal contacts on thin films and do not necessarily translate to measuring contact resistance on bulk TE materials. The authors present a measurement technique that precisely measures contact resistance on bulk TE materials by making and testing stacks of bulk, metal-coated TE wafers using TE industry-standard processes. An equation that uses the Z of the stacked device to extract the contact resistance is used to reduce the sensitivity to resistivity variations of the TE material. Another advantage of this technique is that it exploits realistic TE device manufacturing techniques and results in an almost device-like structure. The lowest contact resistivity measured was 1.1 × 10−6 Ω cm2 and 1.3 × 10−6 Ω cm2 for n- and p-type materials, respectively using a newly developed process at 300 K. The uncertainty in the contact resistivity values for each sample was 10% to 20%, which is quite good for measurements in the 10−6 Ω cm2 range.

Practical electrical contact resistance measurement method for bulk thermoelectric devices

ABSTRACTAs thermoelectric (TE) element length decreases, the impact of contact resistance on TE device performance grows more significant. In fact, for a TE device containing 100-μm tall Bi2Te3TE elements, the figure of merit ratio (ZTDevice/ZTMaterial) drops from 0.9 to 0.5 as the contact resistivity increases from 5 x 10-07 to 5 x 10-06 Ω-cm2. To understand the effects of contact resistance on bulk TE device performance, a reliable experimental measurement method is needed. There are many popular methods to extract contact resistance such as Transmission Line Measurements (TLM) and Kelvin Cross Bridge Resistor method (KCBR), but they are only well-suited for measuring metal contacts on thin films and do not necessarily translate to measuring contact resistance on bulk thermoelectric materials. The authors present a new measurement technique that precisely measures contact resistance (on the order of 5 x 10-07 Ω-cm2) on bulk thermoelectric materials by processing stacks of bulk, metal-coated TE wafers using TE industry standard processes. One advantage of this technique is that it exploits realistic TE device manufacturing techniques and results in an almost device-like structure, therefore representing a realistic value for electrical contact resistance in a bulk TE device. Contact resistance measurements for metal contacts to n- and p-type Bi2Te3 alloys are presented and an estimate of the accuracy of the measurements is discussed.

ErAs epitaxial Ohmic contacts to InGaAs/InP

We report epitaxial ErAs semimetal Ohmic contacts onto n-type In0.53Ga0.47As grown on InP. The contacts were formed by molecular beam epitaxial growth of ErAs on InAs/InGaAs. Transmission line measurements showed minimum specific contact resistivities of 1.5±0.4 Ω μm2 (horizontal specific contact resistivity ρH, 4.20 Ω μm) for the ErAs/InAs/InGaAs contact. The extracted contact resistance is larger than the true value because of the lateral oxidation of ErAs. The contacts degrade over time and at elevated temperatures because of the oxidation of the ErAs, making it difficult to use as surface contacts, but they are suitable as low-resistance buried contacts.

Low-resistance titanium/n-type silicon (1 0 0) contacts by monolayer selenium passivation

Low-resistance Ohmic contacts fabricated by selenium passivation between titanium and n-type silicon (1 0 0) substrates have been characterized by the four-point probe and circular transmission line method. Selenium passivation terminates dangling bonds on the Si(1 0 0) surface and reduces the Schottky barrier height between Ti and n-type Si(1 0 0) substrates. Sheet resistance of the Ti–Si contacts on Se-passivated 1019 cm−3 doped Si substrates shows a ∼30% reduction as compared with control samples. Accordingly, the extracted contact resistance is reduced by about an order of magnitude for samples with different Ti thicknesses and different annealing temperatures. A 29-times reduction in contact resistivity is achieved by Se passivation on highly-doped Si-on-insulator substrates with a 500 Å un-doped Si buffer layer.

Low-resistance Ti/n-type Si(100) Contacts by Monolayer Se Passivation

Low-resistance contacts fabricated by selenium passivation between Ti and n-type Si(100) substrates have been characterized by low-temperature I-V, four-point probe and circular transmission line methods. The Ti-Si contacts on Se- passivated samples demonstrate a significant reduction in Schottky barrier height over control samples in low- temperature I-V. Sheet resistance of the contacts on Se- passivated 1019 cm-3 doped n-type Si(100) substrates shows a 30% reduction as compared with control samples. Accordingly, the extracted contact resistance decreases by about one order of magnitude for samples with different Ti thicknesses and different annealing temperatures. A 125%-2900% reduction in contact resistivity is achieved by Se passivation on highly- doped n-type SOI substrates with 500 Aå un-doped Si buffer layer. The reduction in contact resistance is attributed to the minimization of interface states between Ti and Si(100) surface.