External Inductor Research Articles

MUTUAL EXTERNAL INDUCTANCE IN STRIPLINE STRUCTURES

Abstract—The Method of Edge Currents (MEC) proposed in our previous paper [1] is applied herein for calculating the mutual external inductance associated with fringing magnetic fields that wrap ground planes of a stripline structure. This method employs a quasi-static approach, image theory, and direct magnetic field integration. The resultant mutual external inductance is frequency-independent. The approach has been applied to estimating mutual inductance for both symmetrical and asymmetrical stripline structures. Offset of the signal trace from the centered position both in horizontal and vertical directions is taken into account in asymmetrical structures. The results are compared with numerical simulations using the CST Microwave Studio Software.

Resonance impedance sensing of human blood cells

A challenging problem in alternating current (AC) impedance sensing of particles (e.g., blood cells in plasma) with micro electrodes is that with the shrinking of electrode surface area the electrode double layer capacitance decreases. This double-layer capacitor dominates the system impedance in low frequency range, while the parallel stray capacitor dominates the system impedance in high frequency range. Hence the sensitivity for particle sensing for micro impedance sensors decreases over a wide frequency range. In this paper, we propose an approach to solve the problem. The idea is to use resonant sensing by connecting an external parallel inductor to the system. At the resonant frequency, the capacitive components in the system are nullified by the inductor, leaving the channel impedance (including the particle impedance) to be a major component in the system impedance. We then successfully demonstrate this idea by sensing 5μm polystyrene beads. More important, this technique is extended to sensing blood cells in diluted human whole blood and leukocyte-rich plasma. The sensitivity can be improved by two orders of magnitude over more than three decades in frequency domain. The measured signal peak height histogram at low frequency matches well with known volume distribution of erythrocytes and leukocytes.

Measured CMOS Switched High-Quality Capacitors in a Reconfigurable Matching Network

Switched capacitors are here investigated for use in reconfigurable matching networks, particularly for digital video broadcasting-handheld (DVB-H) frequencies. A 0.13-μm CMOS circuit is evaluated through both simulations and measurements. Source grounded nMOS transistors are used to switch high-quality metal capacitors located above metal layer 8. The quality factor and tuning range depend on frequency, switch voltage, capacitor size, and transistor width. There is a clear tradeoff between quality factor and tuning range, and measurements show quality factors above 50, 100, and 150 at tuning ranges of 3.9, 2.4, and 1.6, respectively. A reconfigurable matching network with the switched capacitors has been realized using external inductors and the measured matching domain for the DVB-H frequency band is shown. The total loss of the network is 1.0 dB, a result of the high-quality switched capacitors.

Low field magnetoimpedance in the GHz range

In this paper we investigate different aspects of the high-frequency magnetoimpedance at low fields. In the first place, we will study this effect from a phenomenological point of view, comparing it with the low-frequency microwave absorption. The results, discussed in terms of an analytical description of the experiments, prove that both effects respond to the same physical causes. In the second place, we will explore the potential of the high-frequency GMI for sensing applications. The measurements, performed at 3 GHz, show that the sensitivity of the magnetoimpedance only drops due to the growth of the external inductance. However, after a proper minimization of the imaginary part (achieved by means of a matching network), the GMI proves to be as sensitive as it is in the hundreds of MHz.

Capacitance–Voltage Measurement Method for Ultrathin Gate Dielectrics Using LC Resonance Circuit

The capacitance-voltage (C-V) measurement method using the LC resonance circuit (LC resonance method) for ultrathin gate dielectrics having large leakage current is demonstrated. In the LC resonance method, only an external inductance and a resistance and a simple equivalent electrical circuit of MOS devices are employed. External inductance can be optimized using the equivalent quality factor. At each gate voltage bias point,parameters of MOS equivalent circuit are determined by fitting the calculation results to the measured impedance-frequency characteristics at the resonance frequency point. Total resistance value of MOS equivalent circuit that is determined from the dc gate current-gate voltage characteristics can be a good help in the fitting sequence. The rms error of calculated and measured impedance-frequency characteristics is used for the fitting verification. The sensitivity of rms error to the variation in MOS capacitance value is discussed to determine the accuracy of the LC resonance method. C-V measurements of both thick (EOT=7.0 nm) and thin (EOT=1.2/spl bsol/ nm) gate dielectrics are demonstrated and the electrical oxide thickness (EOT) values are extracted from the C-V characteristics. Comparison between the LC resonance method and the other C-V measurement methods is also made with respect to C-V measurement results to show the good applicability of the LC resonance method.

Investigation of attenuation increase at lower-side frequency bands for highly-integrated SAW modules

High attenuation characteristics are required at transmitter frequency bands, i.e. lower-side frequency ranges, for receiver surface acoustic ware (SAW) filters especially used in CDMA systems, where transmission and reception are performed simultaneously. Demonstrated is the possibility of new chip-level improvement for attenuation characteristics at these bands without external inductors and capacitors.

Micropower Circuits for Bidirectional Wireless Telemetry in Neural Recording Applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.

Ultra-low power transmit/receive ASIC for battery operated ultrasound measurement systems

Absract This paper describes the design of the complete transmit and receive electronics circuitry for a piezoelectric transducer in one single ASIC. The chip will be one building block in a thumb size battery operated ultrasound measurement system. The main design target has been to achieve extremely low power consumption while keeping the number of external components minimal. To overcome the dynamic range limitations imposed by a battery supply an on-chip boost converter uses one external inductor to generate up to 40 V for excitation of the transducer. The transducer itself is used as a storage capacitor, whereafter it is rapidly discharged to generate an ultraso und pulse. An on-chip amplifier with intermittent operation is controlled by a state machine and used to amplify incoming echoes. The chip has been

An adaptive impedance tuning CMOS circuit for ISM 2.4-GHz band

The difficulties encountered in matching an antenna to its optimal impedance are reduced with an adaptive 0.35-/spl mu/m CMOS circuit based on several switched shunt capacitors arranged in capacitor banks and on a few external series inductors. As high-quality inductors are difficult to obtain in CMOS, the inductors are placed either in an low-temperature cofired ceramic (LTCC) substrate or is a lumped component outside the core circuit. The circuits, presented here through a range of simulations, are optimized to function within the ISM 2.4-GHz band, but the general approach employed to improve matching can be used for other frequency bands as well. The circuits discussed provide a VSWR/spl les/2 match for every impedance with VSWR/spl les/5. There is a 1-dB power loss for a perfect 50 /spl Omega//spl rarr/50 /spl Omega/ transformation, a break-even point at VSWR=1.5, and a 3-dB increase in delivered power for VSWR= 4.3.

Electric Properties of Ti<sub>3</sub>SiC<sub>2</sub> at High Frequency Alternating Current

Bulk Ti3SiC2 material with 95 wt% of purity was synthesized by hot pressing from Ti, SiC and graphite powders. This work focuses on the electric properties of Ti3SiC2 at high frequency alternating current using a specific clamp device. The result shows that Ti3SiC2 exhibits an electric property of inductance (the order of magnitude is about 10-8 H at 1 ~ 40 MHz), which indicates that Ti3SiC2 shows a stronger electric property of metal rather than that of common ceramics. In this study, the equation to calculate the external inductance of nonferromagnetic metal is also applicable to Ti3SiC2 material at high frequency.

A Method for the Measurement of the Resistance of Electrolytic Solutions

We present a method and the corresponding instrumentation to measure the electric resistance of electrolytic solutions in conductivity cells. In this method we use a cylindrical cell and follow the simplest electrical model for an electrochemical cell, which is the electrolyte resistance in series with double-layer capacitance. By adding an external inductance to the real cell it is possible to use the phenomenon of electric resonance in order to cancel the effects of the double-layer capacitance in electrolyte-electrode interfaces, separating the solution resistance during the measurement process. This is a very precise method for obtaining an absolute measurement of the resistance of electrolytic solutions and their conductivity, without using standard chemical solutions. We show the excellent agreement of our resistance measurement and its associated conductivity made for KCl, , with the corresponding standard value.

Effects of the Parasitics on the Time Response of RCE-PDs

Resonant cavity enhanced photodetectors (RCE-PDs) are promising candidates for applications in high-speed optical communications and interconnections. However, because parasitics effects of these high-speed photodetectors can significantly degrade the performance of the photodetector, then they must be carefully considered. Here, an accurate model for the time response of the RCE-PDs that includes the effects of their parasitics is presented. The effects of an inductor that may be added in series with the load resistor are also studied and it is shown that the external inductor can improve the performance of the photodetector because it compensates some of the degradations resulting from capacitive parasitics. The effects of the parasitics have been investigated for different dimensions of the photodetectors, different values of both the load resistance and the added inductor and also for different multiplication gains for the case of RCE-avalanche photodetectors.

Analysis and Circuit Modeling of Waveguide-Separated Absorption Charge Multiplication-Avalanche Photodetector (WG-SACM-APD)

Waveguide photodetectors are considered leading candidates to overcome the bandwidth efficiency tradeoff of conventional photodetectors. In this paper, a theoretical physics-based model of the waveguide separated absorption charge multiplication avalanche photodetector (WG-SACM-APD) is presented. Both time and frequency modeling for this photodetector are developed and simulated results for different thicknesses of the absorption and multiplication layers and for different areas of the photodetector are presented. These simulations provide guidelines for the design of these high-performance photodiodes. In addition, a circuit model of the photodetector is presented in which the photodetector is a lumped circuit element so that circuit simulation of the entire photoreceiver is now feasible. The parasitics of the photodetector are included in the circuit model and it is shown how these parasitics degrade the photodetectors performance and how they can be partially compensated by an external inductor in series with the load resistor. The results obtained from the circuit model of the WG-SACM-APD are compared with published experimental results and good agreement is obtained. This circuit modeling can easily be applied to any WG-APD structure. The gain-bandwidth characteristic of WG-SACM-APD is studied for different areas and thicknesses of both the absorption and the multiplication layers. The dependence of the performance of the photodetector on the dimensions, the material parameters and the multiplication gain are also investigated.

Series resonant sustain driver and reset circuit composition using a single voltage source for an efficient plasma display

A novel sustain driver employing an energy recovery function and a useful reset circuit composition are proposed for efficient driving of a plasma display panel. The proposed sustain driver uses a series resonance between an external inductor and a panel to recover the energy dissipated by a capacitive displacement current of PDP. It consists of four switching devices, an inductor, and external capacitors, which supply sustain voltage sources. Although the amplitude of an input voltage source is twice as high as that of conventional sustain drivers, average voltage stress imposed on power switching devices is nearly same in their values. Moreover, the input voltage source can be directly applied for the use of a reset voltage source. Owing to this scheme, the proposed sustain driver and the embedded reset circuit have a simple configuration. The operational principle and design example are given with theoretical analyses. The validity of the proposed drive system is verified through computer-aided simulations and experiments using a prototype equipped with a 7.5-in.-diagonal AC plasma display panel.

Resonant clocking using distributed parasitic capacitance

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.

Series resonant sustain driver and reset circuit composition using a single voltage source for an efficient plasma display

A novel sustain driver employing an energy recovery function and a useful reset circuit composition are proposed for efficient driving of a plasma display panel. The proposed sustain driver uses a series resonance between an external inductor and a panel to recover the energy dissipated by a capacitive displacement current of PDP. It consists of four switching devices, an inductor, and external capacitors, which supply sustain voltage sources. Although the amplitude of an input voltage source is twice as high as that of conventional sustain drivers, average voltage stress imposed on power switching devices is nearly same in their values. Moreover, the input voltage source can be directly applied for the use of a reset voltage source. Owing to this scheme, the proposed sustain driver and the embedded reset circuit have a simple configuration. The operational principle and design example are given with theoretical analyses. The validity of the proposed drive system is verified through computer-aided simulations and experiments using a prototype equipped with a 7.5-in.-diagonal AC plasma display panel.

Factors affecting energy deposition and expansion in single wire low current experiments

Single wire experiments were performed on a low current pulse generator at Cornell University. A 220 nF capacitor charged to 15–25 kV was used to drive single wire experiments. The capacitor and wire holder were connected in series through an external variable inductor to control the current rise rate. This external series inductance was adjustable from 0.2 to 2 μH. When coupled with the range of charging voltages this results in current rise rates from 5 to 50 A/ns. The current heated the wire through liquid and vapor phases until plasma formed around the wire. Energy deposition and expansion rates were measured as functions of the current rise rate. These results indicated better energy deposition and higher expansion rates with faster current rise rates. Effects of the wire-electrode connection method and wire polarity were also studied.

Novel low-frequency oscillation in a radio-frequency inductively coupled plasma with tuned substrate

The rf self-bias on the substrate in a rf inductively coupled plasma is controlled by varying the impedance of an external tuning inductor and capacitor network inserted between the substrate and the ground. In term of variations of tuned substrate self-bias (Vtsb) with tuning capacitance (Ct), three characteristic regions, namely continuous, instable, and bistable regions are found, corresponding to low, moderate, and high discharge power at a constant gas pressure, respectively. A novel self-oscillation observed in the instable region occurs only within a limited domain of Ct. With the increment in Ct, the self-oscillation frequency increases while its amplitude decreases. Near the boundary of the instable and bistable regions, the self-oscillations shift downward and upward at lower and higher Ct, respectively. The possible mechanism for the self-oscillation is discussed.

The Inductance Model of Coupled High-Tc Superconducting Microstrip Lines

A simple analytical model of odd and even mode external inductance and kinetic inductance for coupled high-temperature superconducting (HTS) microstrip lines is developed. The kinetic inductance model is derived with the extended incremental inductance rule which is applied in a different way for different conductor thickness. The odd and even mode inductance, self- and mutual inductance, characteristic impedance, and attenuation constant are computed with the presented model expressions and the results agree well with that in published literature.

Resonant 90 degree shifter generator for 4-phase trapezoidal adiabatic logic

Abstract. Many adiabatic logic families make use of multi phase trapezoidal or sinusoidal power clocks to recover the energy stored in the load capacitances. A key aspect for the evaluation of the performance of adiabatic logic is then the study of a system that includes the power clock generator. A four-phase trapezoidal power clock generator, according to the requirements of the most promising architectures, namely the ECRL and PFAL, has been designed and simulated. The proposed circuit, realized with a double-well 0.25 µm CMOS technology and external inductors, is a resonant generator designed to oscillate at a frequency of 7 MHz, which is within the optimum frequency range for adiabatic circuits realized with this CMOS technology. The generator has been simulated with the equivalent load of fifty 1-bit adders and the operating behavior of a 4-bit adder has been evaluated. The key aspects of a generator for adiabatic logic are its power consumption and the phase relationships between its output signals. The proposed generator has a conversion efficiency higher than 80%, and it is robust with respect to variations of technology parameters. The four power supplies exhibit the correct relationship of phase also in the presence of no equally distributed loads.