External Base Resistance Research Articles

Investigation of Disilane-Based SiGe-HBT Layers for Low External Base Resistances

In the past decade there has been increased interest in utilizing SiGe-heterojunction bipolar transistors (SiGe-HBT) and in particular SiGe-BiCMOS technologies for applications in the mm-and sub-mm-wave range. High data rate communication systems and optical networks for >100Gb/s, industrial and automotive sensors at 120 GHz for velocity and position control as well as imaging systems at >160 GHz for medical and security systems are some examples for these fields of application. Key elements for the continuous improvement of the high frequency performance of SiGe-HBTs are the scaling of vertical and lateral dimensions as well as design optimization to achieve reduced parasitics. In particular the maximum oscillation frequency fmax could be increased in the last years above 0.5 THz. Beside a sufficient high cut-off frequency fT, a reduced base-collector capacitance CBC and low base resistance RB are beneficial for the fmax performance of a SiGe-HBT. In this work we investigate the behavior of the external base resistance RBext for two different epitaxial processes used in SiGe-HBTs with a silane- (SiH4) and disilane-based (Si2H6) precursor. The SiGe-layers were treated by various rapid thermal annealing (RTA). We processed different wafers with an oxide stack usually used in a standard SiGe-BiCMOS process. After the release of certain silicon regions by reactive-ion-etching the epitaxial layers were deposited. First a selective epitaxial silicon buffer was grown within oxide-free windows followed by non-selective growth of a silicon layer, the in-situ boron doped SiGe base layer and an on top silicon cap layer. For the disilane-based process the SiGe layer grows in an amorphous phase whereas for the silane-based process a poly-crystalline film is formed. The growth of the whole Si-SiGe-Si stack was adapted for disilane process in order to reach the same layer thicknesses for both variants inside oxide free windows (single-crystalline regions) as for the original silane-based process. Sheet resistance (Rs) measurements were performed on 49 points across a wafer on the poly crystalline SiGe layer on an oxide. Figure 1 shows the Rs of silane-based (#1) and disilane-based (#3) SiGe-layer after a rapid thermal annealing at 1010°C for 12s. We observe a decrease of Rs by 60% in comparison to the silane-based SiGe-layer. Even for a reduced annealing temperature of 950°C (#2) the Rs dropped down around 30% in comparison to the silan-based variant. Moreover the standard deviation of the sheet resistance in the poly-crystalline regions across the wafer becomes significantly smaller and decreased by a factor of six down to approximately 50 Ohm/square for the disilane-based SiGe stack. Secondary-ion-mass-spectroscopy (SIMS) measurements were used to characterize the boron doping and SiGe-profile inside the crystalline and poly-crystalline regions of the wafers. In the poly crystalline region the germanium and boron concentration of the disilane-based process corresponds to the distribution of the single crystalline region. However we obtain a difference in the doping distribution after epitaxy (Fig. 2a) in comparison to the silane-based process. This difference becomes more significant after the RTA and we observe a quite homogeneous distribution of Ge and boron for the silane-based SiGe-stack whereas a steeper doping is within poly-crystalline layers for the disilane-based process (Figure 2b). We address this disparity in the Ge and boron distribution to differences in the diffusion behavior for the disilane-based layer stack due to i) the deposition as an amorphous Si/SiGe/Si layer and ii) the grain size of the poly-crystals after the final RTA. For our operation point the loading effect during the disilane-based epi-process leads to a 40% increased boron dose in the external base region compared to the silane-based process and without increasing the B doping inside the single crystalline region. This is beneficial for the behavior of RBext. Finally we applied both variants in a standard SiGe-BiCMOS flow. The overall performance of the SiGe-HBT depends of course on several other aspects like base-emitter and base-collector capacitances and the influence of changing one parasitic component has to be carefully evaluated. Nevertheless the external base resistance as well as the contact resistance dropped by 55% and 45%, respectively, for the disilane-based process and show the benefits for the use of this type of epitaxial layer depositions in advanced SiGe-HBTs. Figure 1

Investigation of Disilane-Based SiGe-HBT Layers for Low External Base Resistances

In this work we study different SiGe epitaxial processes for the base realization of a heterojunction bipolar transistor. In particular we investigate the poly SiGe layer of external base contact region. Silane (SiH4) and disilane (Si2H6) based precursors were used for a chemical vapour deposition (CVD) process of the Si/SiGe/Si layer stack. Sheet resistances of the poly SiGe layer as well as the boron doping and germanium distribution before and after different rapid thermal annealing steps were analyzed. We show that for equal doping profiles in the single crystalline region and minor differences in the thickness of the poly SiGe region the use of a disilane based precursor is beneficial for a reduced external base resistance. Sheet resistance measurements a decrease by more than 60% with respect to the standard silane based SiGe layer.

Advanced Heterojunction Bipolar Transistor for Half-THz SiGe BiCMOS Technology

The high-frequency performance of a novel SiGe heterojunction bipolar transistor (HBT) module with monocrystalline base link is investigated in an industrial 0.13-μm BiCMOS environment. The main feature of this new HBT module is a significant reduction of the external base resistance as shown here by direct comparison with a conventional double-poly-silicon technology. Peak f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> /f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> values of 300/500 GHz are achieved. A minimum current-mode logic ring oscillator gate delay of 1.8 ps and a record operation frequency for a SiGe static frequency divider of 161 GHz are demonstrated.

Improved External Base Resistance Extraction for Submicrometer InP/InGaAs DHBT Models

An improved direct parameter extraction method is proposed for III-V heterojunction bipolar transistor (HBT) external base resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bx</sub> extraction from forward active <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters. The method is formulated taking into account the current dependence of the intrinsic base-collector capacitance found in III-V HBTs with a fully depleted collector. It is shown that the real part of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> reduces to the external base resistance at the collector current <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ic</i> = <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ip</i> /(1 - <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> ), where <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ip</i> is a characteristic current and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> is the zero-current distribution factor given as the ratio of the emitter to the collector area. The determination of the parameters <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ip</i> and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> from experimental <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters is described. The method is applied to high-speed submicrometer InP/InGaAs DHBT devices and leads to small-signal equivalent circuit models, which accurately predicts the measured <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameters as well as the maximum stable power gain/maximum available power gain in the frequency range from 40 MHz to 110 GHz.

Scalable Approach for HBT's Base Resistance Calculation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents a detailed investigation of the dual base method for intrinsic and extrinsic HBT's base resistance extraction that is of utmost importance for process monitoring and device modeling purpose. Ring emitter test structures layout, dc measurement conditions, and extraction methodology have been improved to get reliable results. A particular attention has been drawn to the external base resistance extraction and the effect of parasitic resistances is highlighted. The method has been generalized for an extraction of the base resistance specific parameters using any number of geometries (widths and lengths) and therefore demonstrates the base resistance scalability. This method is applied to a ST state-of-art fully self aligned double poly BiCMOS SiGeC technology, and results are discussed. </para>

12-ps ECL using low-base-resistance Si bipolar transistor by self-aligned metal/IDP technology

A self-aligned metal/IDP (SMI) technology is proposed to reduce the external base resistance and to enable fabrication of high-speed bipolar transistors. This SMI technology produces a self-aligned base electrode of stacked layers of metal and in situ-doped poly-Si (LDP) with a small thermal budget by selective tungsten CVD. It provides the low base resistance and a shallow link base for the small-collector capacitance and the high-cutoff frequency. The base resistance is reduced to a half that in a transistor having a conventional poly-Si base electrode. A maximum oscillation frequency of 81 GHz and a 12.2-ps gate delay time in an ECL ring oscillator at a voltage swing of 250 mV were achieved by using the SMI technology even with an ion-implanted base.

Carbon-doped base GaAs/AlGaAs heterojunction bipolar transistor grown by metalorganic chemical vapor deposition using carbon tetrachloride as a dopant source

Carbon tetrachloride (CCl4) has been used as a carbon doping source for the base region of a GaAs/AlGaAs Npn heterojunction bipolar transistor (HBT) grown by low-pressure metalorganic chemical vapor deposition (MOCVD). Transistors were fabricated and characterized for dc current gain, emitter-base junction ideality factor, base contact resistance, and external base resistance. Microwave characterization by S-parameter measurement was performed to determine the common emitter current gain and maximum available gain as a function of frequency. Transistors with the base contact area self-aligned to a 3×10 μm emitter finger had a dc current gain as high as 50, an emitter-base junction ideality factor of n=1.2, and a current gain cutoff frequency of ft=26 GHz. Transistors of equal emitter area without self-alignment exhibited dc current gain as high as 86, n=1.2, and ft=20 GHz. A base contact resistance of Rc=2.85×10−6 Ω cm2 and an external base sheet resistance of Rs=533.4 Ω/⧠ were measured. These preliminary results indicate that carbon doping from CCl4 may be an attractive substitute for Zn or Mg in GaAs/AlGaAs HBT structures grown by MOCVD.

High‐performance BIMOS using self‐aligning polysilicon electrode

AbstractTo increase the speed of Hi‐BiCMOS, the process of forming an electrode which simultaneously reduces both parasitic capacitance and parasitic resistance in MOSFET's and bipolar transistors was investigated.Since the etching rate of highly doped polycrystalline silicon is higher than undoped polycrystalline silicon, arsenic‐doped polycrystalline silicon on the gate and emitter electrodes can be etched selectively. Self‐aligned polycrystalline silicon electrode technology (SPEL) using this phenomena was proposed.When the As concentration in polycrystalline Si is higher than 4 × 1020 cm−3, the doped polycrystalline Si is etched 10 times faster than undoped polycrystalline Si if plasma etching based on chlorine radicals is carried out.Using this process, the drain capacitance of the MOSFET was reduced one‐half to one‐third that of conventional devices. In bipolar transistors, collector resistance was reduced by a factor of 2 and the external base resistance was reduced by a factor of 3. As a result of simulating the performance of the device formed by the SPEL process, the gate delay time in a dual input NAND BiCMOS was 0.19 ns under no‐load condition while the gate delay time of the conventional device was 0.26 ns; that is, the speed of the SPEL device is 25 percent faster than that of the conventional device.

High Frequency Transistor Inverter with CT

The commutation mechanism of high-frequency transistor inverters with a current transformer was studied. The current transformer eliminated the need for dead time in the commutation time, as in the usual procedure. It was also found that storage time can be reduced by connecting an external base resistance and that the storage time can be used for effective switching. However there is a trade off here with such parameters as the oscillation conditions and fall time.

Generalized Model Analysis of Ionizing Radiation Effects in Semiconductor Devices

The necessity of analyzing complex semiconductor device behavior in the radiation environment requires improved analytical methods for accurate representation. The purpose of this discussion is to present work done on the applicability of the Linvill lumped model in a generalized model analysis. The advantages of the lumped model technique include flexibility in detail of device representation (i.e., accuracy), an intimate coupling to the well known radiation effects in bulk semiconductor material, and a unified analytical technique for a wide range of devices. It is shown that the lumped model analysis provides an effective technique for analyzing simple as well as complex devices in a pulsed ionizing radiation environment. Included is the representation of a simple p-n junction diode, a grown-junction transistor; and a planar-diffused transistor with its monolithic-chip substrate and isolation junction. The lumped-model behavior of the diode and grown junction transistor is compared to previously available analytical results. Using measured parameter values, the quantitative lumped-model predictions are compared to experimentally observed transient radiation response. The transistor response is investigated as a function of quiescent emitter current and external base resistance. The effect of the substrate junction in the monolithic-chip transistor is qualitatively presented as a function of the transistor parameters and the substrate proximity.

Flicker noise in transistors

Measurements of the noise voltage appearing at the ac open-circuited emitter of a transistor with its collector ac grounded and with both an external base resistance and the operating point as parameters can be used to study the location of flicker-noise sources in transistors. A general flicker-noise model is assumed. It is shown by this method of measurement that for many modern transistors the flicker-noise sources are adequately represented by a single noise current generator connected in parallel with the emitter-base junction. The method permits evaluation of the magnitude of both the correlated and uncorrelated parts of a possible collector-base flicker-noise current generator as well as measurement of the emitter-base generator.