Exposed Pad Packages Research Articles

Package Reliability and Integrity Improvements for a Thermally Enhance Non-Conductive Die Attach Adhesive for ASIC Devices on Exposed Pad Packages

Abstract Polymers being used in a plastic-encapsulated integrated circuit (IC) package exposed to a humid environment absorbed moisture and expand resulting to a so called delamination failure. Weak or imperfect adhesions between the interfaces of the mold compound and adhesive unto the leadframe surface are often the main sources of these failures. In response to automotive requirements and to ensure excellent package reliability and integrity, delamination in all interfaces should then be eliminated. Thus the primary objective of this work is to fulfill the no delamination criteria in all interfaces after moisture soak for an exposed pad package. To satisfy these requirements, activities includes leadframe design improvements, surface enhancement and bill-of-material changes. With the design improvements implemented, still the material compatibility plays an important role in achieving improved package reliability.

Moldflow simulation of an exposed pad leaded package

A study has been conducted for epoxy mold compound filling for a 48 lead exposed pad package. The leadframe design contains a small gap feature where it is critical to evaluate void estimates. A modeling method is being discussed to accurately predict the flow front behavior and make void percentage estimates. With improved design, void percentage significantly goes down as predicted by models. The paper contains detailed methodology for creation of CAD model with standard leadframe drawing and final analysis using a defined gate area. Fill time contours shows significant improvement comparing two designs with 35 μm and 65 μm gap feature.

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.

On chip–package stress interaction

In this paper, the interaction between chip and package is investigated. A series of experiments are conducted to investigate the effect of the package type on occurrence of passivation cracks in IC structures. Virtual prototyping is used to generate more accurate and efficient stress design rules for IC backend structures, in combination with packaging processes and geometry. The addressed failure mode of passivation cracks is found to depend on the package type or family: for exposed pad packages this failure mode is easier to occur. It is demonstrated that for successful development of IC backend structures and processes, it is essential to take into account the influence of the package in the earlier phase of IC backend development. The so-called integral design rules, accounting for all the major loading sources and history of the complete product creation process has to be used for the development of new generation semiconductors devices.

Driving Mechanisms of Delamination Related Reliability Problems in Exposed Pad Packages

Exposed pad packages were introduced in the late 1980s and early 1990s because of their excellent thermal and electrical performance. Despite these advantages, the exposed pad packages experience a lot of thermo-hygro-mechanical related reliability problems during qualification and testing. Examples are die lift, which occurs predominantly after moisture sensitivity level conditions, and die-attach to leadframe delamination leading to downbond stitch breaks during temperature cycling. In this chapter, nonlinear finite element (FE) models using fracture mechanics based J-integral calculations are used to assess the reliability problems of the exposed pad package family. Using the parametric FE models any geometrical and material effects can be explored to their impact on the occurrence diepad delamination, and dielift. For instance the impact of diepad size is found to be of much less importance as the impact of die thickness is. Using the fracture mechanics approach, the starting location for the delamination from thermo-hygro-mechanical point of view is deducted. The results indicate that when diepad delamination is present, cracks are likely to grow beneath the die and dielift will occur. The interaction between dielift and other failure modes, such as lifted ball bonds, are not found to be very significant. The FE models are combined with simulation-based optimization methods to deduct design guidelines for optimal reliability of the exposed pad family.