Execution Of Multiple Instructions Research Articles

Suppression of Crosstalk in Quantum Computers Based on Instruction Exchange Rules and Duration

Crosstalk is the main noise source in quantum computing devices. In quantum computation, the parallel execution of multiple instructions will cause crosstalk, destroy the quantum state, and cause the program to fail to execute correctly. Overcoming the influence of crosstalk is a key requirement for quantum error correction and large-scale fault-tolerant quantum computing. This paper presents a method to suppress crosstalk in quantum computers based on multiple instruction exchange rules and duration. Several Benchmarks experiments verify the effectiveness of the proposed method. Compared with the prior techniques, the fidelity of the proposed method is improved by 15.97% on average.

Suppression of Crosstalk in Quantum Circuit Based on Instruction Exchange Rules and Duration.

Crosstalk is the primary source of noise in quantum computing equipment. The parallel execution of multiple instructions in quantum computation causes crosstalk, which causes coupling between signal lines and mutual inductance and capacitance between signal lines, destroying the quantum state and causing the program to fail to execute correctly. Overcoming crosstalk is a critical prerequisite for quantum error correction and large-scale fault-tolerant quantum computing. This paper provides an approach for suppressing crosstalk in quantum computers based on multiple instruction exchange rules and duration. Firstly, for the majority of the quantum gates that can be executed on quantum computing devices, a multiple instruction exchange rule is proposed. The multiple instruction exchange rule reorders quantum gates in quantum circuits and separates double quantum gates with high crosstalk on quantum circuits. Then, time stakes are inserted based on the duration of different quantum gates, and quantum gates with high crosstalk are carefully separated in the process of quantum circuit execution by quantum computing equipment to reduce the influence of crosstalk on circuit fidelity. Several benchmark experiments verify the proposed method's effectiveness. In comparison to previous techniques, the proposed method improves fidelity by 15.97% on average.

Design and Assertion Based Verification of RISC-V Processor Subsystems

RISC-V is an open, free standard architecture. As its open-source architecture, it can be used in multiple applications like embedded processors, IoT, artificial intelligence, machine learning, military and defense applications. The parameters like throughput, performance, high speed etc., become essential in designing processor architecture. Pipelining is one such unique feature supported by RISC-V ISA, which basically involves the execution of multiple instructions in single cycle. This feature helps in improving the performance of the processor architecture. RISC-V ISA supports five stages of pipelining they are instruction fetch, instruction decode, execute, memory and write-back stage. The work covered in this paper involves the design and implementation of the subsystems of the RISC-V ISA which are present in different stages of pipeline architecture. The subsystems included in this work are Floating Point Unit (FPU) of Execute stage, Branch Prediction Unit (BPU) of instruction fetch stage, Forwarding Unit of execution stage, Operand Logic of decode stage and Floating-Point register file of Write-back stage. These subsystems are designed using Verilog Hardware Description Language in Xilinx ISE. Followed by the implementation the verification of the floating-point unit and the forwarding unit is performed using System Verilog Assertions in QuestaSim. The Assertion coverage report for the same is extracted.

Compact Keccak Hardware Architecture for Data Integrity and Authentication on FPGAs

ABSTRACT Cryptographic hash functions play a crucial role in networking and communication security, including their use for data integrity and message authentication. Keccak hash algorithm is one of the finalists in the next generation SHA-3 hash algorithm competition. It is based on the sponge construction whose hardware performance is worth investigation. We developed an efficient hardware architecture for the Keccak hash algorithm on Field-Programmable Gate Array (FPGA). Due to the serialization exploited in the proposed architecture, the area needed for its implementation is reduced significantly accompanied by higher efficiency rate. In addition, low latency is attained so that higher operating frequencies can be accessed. We use the coprocessor approach which exploits the use of RAM blocks that exist in most FPGA platforms. For this coprocessor, a new datapath structure allowing parallel execution of multiple instructions is designed. Implementation results prove that our Keccak coprocessor achieves high performance in a small area.

Energy-effective issue logic

The issue logic of a dynamically-scheduled superscalar processor is a complex mechanism devoted to start the execution of multiple instructions every cycle. Due to its complexity, it is responsible for a significant percentage of the energy consumed by a microprocessor. The energy consumption of the issue logic depends on several architectural parameters, the instruction issue queue size being one of the most important. In this paper we present a technique to reduce the energy consumption of the issue logic of a high-performance superscalar processor. The proposed technique is based on the observation that the conventional issue logic wastes a significant amount of energy for useless activity. In particular, the wake-up of empty entries and operands that are ready represents an important source of energy waste. Besides, we propose a mechanism to dynamically reduce the effective size of the instruction queue. We show that on average the effective instruction queue size can be reduced by a factor of 26% with minimal impact on performance. This reduction together with the energy saved for empty and ready entries result in about 90.7% reduction in the energy consumed by the wake-up logic, which represents 14.9% of the total energy of the assumed processor.

A performance comparison of several superscalar processor models with a VLIW processor

Superscalar and VLIW processors can both execute multiple instructions each cycle. Each employs a different instruction scheduling method to achieve multiple instruction execution. Superscalar processors schedule instructions dynamically, and VLIW processors execute statically scheduled instructions. This paper quantitatively compares various superscalar processor architectures with a very long instruction word (VLIW) architecture developed at the University of California, Irvine. An architectural overview and performance analysis of the superscalar processor models and VIPER, a VLIW processor designed to take advantage of the parallelizing capabilities of percolation scheduling, are presented. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each.