Excellent Phase Linearity Research Articles

Analysis and design of a compact ultrawideband LNA with 2.3 ± 0.1 dB NF and ±14.6 ps group‐delay‐variation in 0.18‐µm CMOS

ABSTRACTA low‐noise figure (NF) and high power gain (S21) 3–10 GHz ultrawideband low‐noise amplifier (UWB LNA) with excellent phase linearity using standard 0.18‐µm CMOS technology is reported. An enhanced π‐match input network is used to achieve wideband input impedance matching. Both high and flat S21 and low and flat NF frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA consumes 18 mW, achieving S11 better than −10 dB for frequency lower than 12.2 GHz and group‐delay‐variation smaller than ±14.6 ps for frequencies 3–10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1–12.5 GHz, which means the corresponding 3‐dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies 3–10 GHz, one of the best NF results ever reported for a 3–10 GHz CMOS UWB LNA. The measured input third‐order intermodulation point (IIP3) is −0.2 dBm at 6 GHz. The chip area is only 0.601 × 0.662 mm2 (i.e., 0.4 mm2) excluding the test pads. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2047–2053, 2014

A low-power, low-noise and high linearity 60 GHz wideband CMOS low-noise amplifier for wireless personal area network (WPAN) systems

A low power and low noise figure (NF) 60 GHz wideband low-noise amplifier (LNA) with excellent phase linearity for wireless personal local network (WPAN) systems using standard 90 nm CMOS technology is reported. To achieve sufficient power gain (S21) and reverse isolation (S12), the LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S11 better than ?10 dB for frequencies 55.1---59.5 GHz, S22 better than ?10 dB for frequencies 55.1---59.4 GHz, S12 better than ?42.6 dB for frequencies 50---64 GHz, and group delay variation smaller than ±13.25 ps for frequencies 50.4---63 GHz. Additionally, high and flat S21 of 9.9 ± 1.5 dB is achieved for frequencies 50.4---62.9 GHz, which means the corresponding 3-dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves minimum NF of 3.88 dB at 55.5 GHz and NF of 4.73 ± 0.85 dB for frequencies 50---63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.

High-Performance Wideband Low-Noise Amplifier Using Enhanced $\pi$-Match Input Network

A low noise-figure (NF) and high power gain (S21) 3 ~ 10 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity using 0.18 μm CMOS technology is reported. An enhanced π-match input network is used to achieve wideband input impedance matching as well as high and flat S21. To achieve low and flat NF, the pole frequency and pole quality factor of the second-order NF frequency response are tuned to approximate the maximally flat condition. The LNA consumes 18 mW, achieving S11 better than -10 dB for frequency lower than 12.2 GHz and group-delay (GD) variation smaller than ±14.6 ps for frequencies 3 ~ 10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1 ~ 12.5 GHz, which means the corresponding 3-dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies of 3 ~ 10 GHz, one of the best NF results ever reported for a 3 ~ 10 GHz CMOS LNA.

A 3.1–10.6‐GHz Current‐Reused CMOS Ultra‐Wideband Low‐Noise Amplifier Using Self‐Forward Body Bias and Forward Combining Techniques

ABSTRACTA 3.1–10.6‐GHz ultra‐wideband low‐noise amplifier (UWB LNA) with excellent phase linearity property (group‐delay variation is only ±19.46 ps across the whole band) using standard 0.18‐µm CMOS technology is reported. Current reused, self‐forward body bias and forward combining techniques are used to achieve low power and high‐power gain (S21). Both high and flat S21 and low and flat noise figure (NF) frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA dissipates 6.93‐mW power and achieves NF of 3.76 at 10 GHz. In addition, the LNA achieves input return loss (S11) smaller than −10.6 dB, and high and flat S21 of 11.02 ± 0.47 dB over the 3.1–10.6‐GHz band. The corresponding figure of merit (FOM) is 3.11 GHz/mW, one of the lowest FOMs ever reported for a 3.1–10.6 GHz CMOS UWB LNA. The measured input third‐order intermodulation point (IIP3) is −3.6 dBm at 6 GHz. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2296–2302, 2013

3.88 dB NF 60 GHz CMOS UWB LNA with small group‐delay‐variation

A low power and low noise figure (NF) 60 GHz low-noise amplifier (LNA) with excellent phase linearity using standard 90 nm CMOS technology is reported. The LNA comprises a common-source (CS) stage followed by a cascode stage and a CS stage. The LNA consumes 14.1 mW, achieving S 11 better than - 10 dB for the frequencies 55.1-59.5 GHz, S 22 better than - 10 dB for the frequencies 55.1-59.4 GHz, and group delay variation smaller than - 13.25 ps for the frequencies 50.4-63 GHz. Additionally, high and flat S 21 of 9.9 ± 1.5 dB is achieved for the frequencies 50.4±62.9 GHz, which means the corresponding 3 dB bandwidth is 12.5 GHz. Furthermore, the LNA achieves a minimum NF of 3.88 dB at 55.5 GHz and an NF of 4.73 ± 0.85 dB for the frequencies 50±63.5 GHz, one of the best NF results ever reported for a 60 GHz CMOS LNA.

5–11 GHz CMOS PA with 158.9 ± 41 ps group delay and low power using current-reused technique

This paper proposes the design of a low group delay and low power ultra-wideband (UWB) power amplifier (PA) in 0.18μm CMOS technology. The PA design employs two stages cascade with inductive peaking technique to provide broad bandwidth characteristic and higher gain while gain flatness can be achieved by connecting inter-stage circuit. A common gate current-reused technique is adopted at the first stage amplifier to achieve good input matching, low group delay and low power. The simulation results show that the proposed PA design has an average gain of 11.5dB with flatness of ±0.4dB from 5–11GHz, while maintaining bandwidth of 4.2–12.3GHz. An input return loss (S11) less than −10.4dB and output return loss (S22) less than −9.5dB, respectively are obtained. The PA design achieves excellent phase linearity (i.e., group delay variation) of ±41ps and only consuming 17mW power from 1.2V supply voltage. A good output 1-dB compression point OP1dB of 3.7dBm is obtained. By using this method, the proposed design has low group delay variation and lowest power among the recently reported UWB CMOS PAs applications.

11.81 mW 3.1–10.6 GHz ultra‐wideband low‐noise amplifier with 2.87 ± 0.19 dB noise figure and 12.52 ± 0.81 dB gain using 0.18 μm CMOS technology

AbstractA 3.1–10.6 GHz ultra‐wideband low‐noise amplifier (UWB LNA) with excellent phase linearity property (group‐delay variation is only ±15.79 ps across the whole band) using standard 0.18 μm CMOS technology is reported.Both high and flat power gain (S21) and low and flat noise figure (NF) frequency responses are achieved by tuning the pole frequencies and pole quality factors of the second‐order gain and NF frequency responses to approximate the maximally flat condition simultaneously. The LNA dissipates 11.81 mW power and achieves input return loss (S11) smaller than −10.25 dB, high and flat S21 of 12.52 ± 0.81 dB, and low and flat NF of 2.87 ± 0.19 dB over the 3.1–10.6 GHz band. To the author's knowledge, this is one of the lowest NFs ever reported for a 3.1–10.6 GHz CMOS UWB LNA. The measured 1‐dB compression point and input third‐order intermodulation point are −16 and −6.2 dBm, respectively, at 6 GHz. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 54:1445–1450, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26813

DC~10.5 GHz complimentary metal oxide semiconductor distributed amplifier with RC gate terminal network for ultra-wideband pulse radio systems

A DC ~ 10.5 GHz complimentary metal oxide semiconductor (CMOS) distributed amplifier (DA) with flat and low noise figure (NF), flat and high power gain (S 21 ) and small group delay (GD) variation for ultra-wideband (UWB) pulse radio systems using standard 0.18 μm CMOS technology is demonstrated. Flat and low NF was achieved by adopting the proposed resistor capacitor (RC) terminal network with 140 Ω terminal resistance over the frequency band of interest (instead of the traditional 50 Ω terminal resistance or the recently proposed resistor inductor (RL) terminal network) for the gate transmission line. Besides, flat and high S 21 was achieved by using cascoded transistors as the gain cell. Over the DC ~ 10.5 GHz band, the DA consumed 29.16 mW and achieved flat and high |S 21 | of 10.5 + 1.4 dB, flat and low NF of 3.2 + 0.3 dB and excellent phase linearity (the GD variation was only +13.8 ps), one of the best NF and phase linearity results ever reported for a CMOS DA or wideband low-noise amplifier (LNA) with bandwidth greater than 7.5 GHz.

A 4.9-dB NF 53.5- to 62-GHz micromachined CMOS wideband LNA with small group-delay-variation

A 53.5- to 62-GHz wideband low-noise amplifier (LNA) with excellent phase linearity property using standard 0.13 μm CMOS technology is reported.To achieve sufficient gain, the LNA is composed of six cascade common-source stages. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3 to −19.5 dB, output return loss (S22) of −13.8 to −27.8 dB, forward gain (S21) of 8.1 to 11.1 dB, and reverse isolation (S12) of −49.9 to −60.2 dB over the 53.5- to 62-GHz-band. The minimum NF (NFmin) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S21 (S21-max) of 13.2 dB (at 58 GHz), 2.1 dB higher than that (11.1 dB) of the STD LNA (at 58.5 GHz). In addition, the ICP LNA achieved NFmin of 4.9 dB (at 61 GHz), 0.5 dB lower than that (5.4 dB) of the STD LNA (at 62 GHz). These results demonstrate the proposed LNA architecture in conjunction with the backside ICP deep-trench technology is very promising for high-performance 60-GHz-band RFIC applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2427–2432, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25500

High efficiency, good linearity, and excellent phase linearity of 3.1-4.8 GHz CMOS UWB PA with a current-reused technique

This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ±135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50 Ω load impedance was achieved with a power consumption of 24-mW.

An 18.85 mW 20–29 GHz wideband CMOS low‐noise amplifier with 3.85 ± 0.25 dB noise figure and 18.1 ± 1.9 dB gain

AbstractA 20–29 GHz wideband CMOS low‐noise amplifier (LNA) with flat and low noise figure (NF), flat and high‐gain (S21), and excellent phase linearity property (group‐delay‐variation is only ±22.6 ps across the whole band) is demonstrated.To achieve flat and low NF, the size, layout, and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was tuned to obtain a slightly under‐damped (flat) NF frequency response. In addition, to achieve flat and high S21 and small group‐delay‐variation, the inductive‐peaking technique was adopted in the current‐reused stage for bandwidth enhancement. The LNA consumed 18.85 mW power and achieved flat and low NF of 3.85 ± 0.25 dB, and flat and high S21 of 18.1 ± 1.9 dB over the 20–29 GHz band of interest. These are the best NF and S21 performances ever reported for a 21.65–26.65 GHz or a 22–29 GHz wideband CMOS LNA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2017–2020, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25380

2.5 dB NF 3.1–10.6 GHz CMOS UWB LNA with small group-delay variation

A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay variation is only ±16.7 ps across the whole band) using standard 0.13 µm CMOS technology is reported. To achieve high and flat gain and small group-delay variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA achieved input return loss (S11) of −17.5 to −33.6 dB, output return loss (S22) of −14.4 to −16.3 dB, flat forward gain (S21) of 7.92±0.23 dB, and reverse isolation (S12) of −25.8 to −41.9 dB over the 3.1–10.6 GHz band of interest. A state-of-the-art noise figure (NF) of 2.5 dB was achieved at 10.5 GHz.

0.18 µm 3.1–10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7±17.4 ps group-delay

A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only ±17.4 ps across the whole band) using standard 0.18 µm CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S11) of −9.7 to −19.9 dB, output return loss (S22) of −8.4 to −22.5 dB, flat forward gain (S21) 11.4±0.4 dB, reverse isolation (S12) of −40 to −48 dB, and noise figure of 4.12–5.16 dB over the 3.1–10.6 GHz band of interest. A good 1 dB compression point (P1 dB) of −7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681×657 µm excluding the test pads.

Minimum phase transfer functions providing a compromise between phase and amplitude approximation

Transfer functions of low-pass filters with no finite transmission zeros are introduced satisfying a number of phase flatness conditions at the origin and providing more stopband rejection than the corresponding Butterworth filters. If only one of the available degrees of freedom is used to shape the passband magnitude response, while all remaining are assigned to phase linearity, the largest fractional banwidth of phase linearity is obtained but the maximum passband loss cannot be specified beforehand and increases with increasing the order of the network. It is shown, however, that assigning two parameters to magnitude requirements in the resulting transfer function almost any prescribed maximum passband loss can be met while still retaining excellent phase linearity over a large part of the passband. In addition, a class of transitional filter functions is obtained the frequency and time domain characteristics of which can be adjusted over a wide range of filter specifications by varying one parameter only. It is shown that the time domain characteristics of these filters compare favorably with those for the well-known transitional Butterworth-Thomson filters.

An audio power amplifier for ultimate quality requirements

A 50 W/4 Ω complementary symmetry audio amplifier concept is described. The amplifier is designed to meet ultimate quality requirements with particular emphasis on lack of transient intermodulation distortion. Excellent phase and amplitude linearity is obtained using low feedback value, class A operation for most of the signal time, and a fully symmetric dc-coupled high frequency design.