Evolutionary Design Of Digital Circuits Research Articles

Encodings and genetic operators for efficient evolutionary design of digital circuits

The performance of evolutionary computation-based methods, such as genetic algorithms, depends primarily on the fitness function. Nonetheless, they are also critically impacted by the choice of the representation of potential solutions and used genetic operators. With this motivation, we analyse the impact of two different circuit encodings used for circuit evolution on the process performance. The main objective is to elect the more appropriate encoding and genetic operators to yield efficient designs regarding the cost function. The first approach is based on genetic programming while the second views circuits as gate maps. Furthermore, we compare the impact of both circuit representations on the evolutionary process. Evolved circuits must implement the exact expected behaviour, yet, they should minimise hardware and time requirements. We show that for the same input/output behaviour, employing both approaches yields circuits of similar characteristics. However, the evolution process is more efficient in the case the second encoding.

Practical and scalable evolution of digital circuits

This paper addresses the scalability problem prevalent in the evolutionary design of digital circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable alternative design methodology for large and complex circuits. Despite the effort by the EHW community to overcome the scalability problems using both direct mapped techniques and developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a modular developmental approach, namely, the Modular Developmental Cartesian Genetic Programming (MDCGP) technique, it is indeed possible to evolve large circuits. As a proof of concept, a 5 × 5 multiplier is evolved for partition sizes of 32 and 64. It is shown that compared to the direct evolution technique, the MDCGP technique provides five times reduction in terms of evolution times, 6–56% reduction in area and improved fault tolerance. The technique is readily scalable and can be applied to even larger partition sizes, and also to sequential circuits, thus providing a promising path to evolve large and complex circuits.