Etching Of Silicon Research Articles

Investigating Quantum Confinement and Enhanced Luminescence in Nanoporous Silicon: A Photoelectrochemical Etching Approach Using Multispectral Laser Irradiation

This study explores electrochemical etching to form porous silicon (PS), which has diverse biomedical and energy applications. Our objective is to gain new insights and drive significant scientific and technological advancements. Specifically, we study the effect of electrochemical etching of P-type silicon using laser irradiation in a hydrofluoric acid (HF) solution. The formation of the nanoscale PS structure can be successfully controlled by incorporating laser irradiation into the electrochemical etching process. The wavelength and power of the laser influence the formation of nanoporous silicon (NPS) on the surface during the electrochemical etching process. The luminous flux is monitored with the help of a customized integrating sphere system and an LED-based excitation source to find the light flux values distributed across the P-type nanolayer PS wafers. Analysis of the NPS and luminescence characteristics shows that the laser bandwidth controls the band gap energy absorption (BEA) phenomenon during the electrothermal reaction. It is demonstrated that formation of the NPS layer can be controlled in this combined laser irradiation and electrochemical etching technique by adjusting the range of the laser wavelength. This also allows for further precise control of the numerical trend of the luminous flux.

Metal Ions’ Dynamic Effect on Metal-Assisted Catalyzed Etching of Silicon in Acid Solution

Metal-assisted catalyzed etching (MACE) technology is convenient and efficient for fabricating large-area silicon nanowires at room temperature. However, the mechanism requires further exploration, particularly the dynamic effect of various ions in the acid-etching solution. This paper investigated the MACE of silicon wafers predeposited with metal nanofilms in an HF-M(NO3)x-H2O etching solution (where M(NO3)x is the nitrate of the fourth-period elements of the periodic table). The oxidizing ability of Fe3+ and NO3− was demonstrated, and the dynamic influence of metal ions on the etching process was discussed. The results show that the MACE of silicon can be realized in various HF-M(NO3)x-H2O etching solutions, such as KNO3, Al(NO3)3, Cr(NO3)3, Mn(NO3)2, Ni(NO3)2, Co(NO3)2, HNO3, and Ca(NO3)2. It is confirmed that the concentration and type of cations in the etching solution affect the etching rate and morphology of silicon. Fe3+ and NO3− act as oxidants in catalytic etching. The fastest etching rate is about 5~6 μm/h in Ni(NO3)2, Co(NO3)2, and Ca(NO3)2 etching solutions. However, a high concentration of K+ hinders silicon etching. This study expands the application of MACE etching solution systems.

Aspect Ratio-Dependent Etching in Silicon using XeF2: Experimental Investigation and Comparative Analysis with Dry Etching Methods

Abstract Silicon machining plays a crucial role in shaping three-dimensional structures for Micro-Electro-Mechanical Systems (MEMS) applications. This study investigates Aspect Ratio Dependent Etching (ARDE) across various silicon etching processes, with a particular focus on Xenon Difluoride (XeF2) etching, in comparison to Reactive Ion Etching (RIE) and Deep Reactive Ion Etching (DRIE).By exploring different etching parameters, the study highlights the presence of ARDE in both plasma and non-plasma etching processes. Additionally, it is demonstrated that ARDE can be modeled by a saturating exponential function through experimental adjustment of parameters, enabling the prediction of etching profiles.

Research on Chip Manufacturing and Fault Detection Technology

In the wave of the digital era, the chip plays a key role in promoting the whole information technology revolution with its core position in the development of world science and technology. As the cornerstone of computing and data processing, the development of chips has promoted the progress of the entire technology field. The chip’s manufacturing is the key to determining the performance and computing power of the whole chip, and fault detection technology in the production process is an important part of determining the product’s quality and cost. Therefore, under the background of Moore’s law approaching the physical limit, how to ensure the yield of chip production while continuing to improve chip performance has become a major challenge for the chip manufacturing industry. Based on this, this paper summarizes the key manufacturing steps of the chip. The chip manufacturing technology is comprehensively sorted from design to silicon wafer manufacturing, photolithography, etching, ion implantation, and other processes. At the same time, the research direction of monocrystalline silicon manufacturing technology and the existing lithography technology are introduced, including optical lithography, extreme ultraviolet lithography, electron beam lithography, and so on. Fault detection technology in chip production has also been introduced. In addition, the chip manufacturing and fault detection technology introduced in this paper is summarized and its future development is prospected, which provides reference and inspiration for promoting the continuous progress of chip technology.

Micropyramidal Si Photonics–A Versatile Platform for Detector and Emitter Applications

AbstractAnisotropic wet etching of silicon (Si) has been known for decades, but the extraordinary capabilities of this technology to provide highly ordered microphotonic arrays have received limited attention in previous studies. It is shown that these capabilities include: i) a unique self‐terminating etching nature − crucial for achieving uniform arrays over centimeter‐scale wafers, ii) an extraordinary smoothness of the slow‐etching (111) planes, and iii) a precise geometry control including the extent micropyramids or micropyramidal voids are truncated. The combination of these properties transforms this technology into a versatile platform for novel detector and emitter applications in Si photonics. The optical properties of such arrays are studied by finite‐difference time‐domain modeling in two realms represented by different boundary conditions (BCs). Periodic BCs result in Talbot self‐images experimentally observed in this work. Perfectly matched layer BCs describe mesoscale interference effects resulting in the subwavelength focusing properties of micropyramids. Enhancements in the performance of mid‐wave infrared (MWIR) focal plane arrays are demonstrated by monolithic integration of Si micropyramids with silicon‐platinum silicide Schottky barrier photodetectors. Finally, it is shown that Si micropyramidal arrays can be used to enhance light extraction and directionality of quantum sources and infrared scene projectors.

Deep cryogenic silicon etching for 3D integrated capacitors: A numerical perspective

One promising approach to increase the capacity density of integral microcapacitors, microsupercapacitors, and microbatteries is three-dimensional structure design, where electrodes are exposed in three dimensions instead of conventional in-plane electrodes. Such structures include nanowires, nanotubes, nanopillars, nanoholes, nanosheets, and nanowalls. In this work, a cryogenic silicon etching process suitable for fabrication of structures with high electrode area is proposed. A numeric model of this process is experimentally calibrated and used for pillar array structure sidewall area optimization. The use of adaptive Runge–Kutta–Fehlberg time integrator allows to achieve almost linear overall computation complexity as a function of simulated etching time, despite the linear increase in conductance computation complexity with depth. A rule for choosing optimal geometric structure parameters under technological constraints is formulated. An optimized trefoil-like structure is proposed, resulting in a total 5.5% increase in sidewall area with respect to the hexagonal array of circular pillars, resulting in 20.33 sidewall area per unit chip area for 30 min long etch or 31.80 for 60 min long etch.

The preliminary study of etching characteristics of atmospheric pressure trifluoromethane plasma jet etching

Abstract The capacitive coupling radio frequency atmospheric pressure plasma jet for silicon etching, through the carrier gas carrying trifluoromethane gas, varying the gas flow rate for plasma etching. It finds the impact of varying gas flow rates on plasma etching and analyzes the resulting two-dimensional and three-dimensional surface topographies using surface profilometer. Experimental findings indicate that at a trifluoromethane flow rate of 250 sccm and a working distance of 6 mm, the etching rate achieves 38.7 μm/min. Notably, the research emphasizes the crucial role of trifluoromethane (CHF3) gas in plasma etching, highlighting its fluorocarbon ratio and chemical structure as primary factors influencing the etching process on monocrystalline silicon. Ultimately, the study proposes a methodology involving trifluoromethane gas for silicon wafer etching, enabling the transformation of micro-patterns onto crystalline silicon using a mask. This research contributes valuable insights into optimizing plasma etching techniques for microfabrication processes in semiconductor technology.

Mechanism of Improving Etching Selectivity for E-Beam Resist AR-N 7520 in the Formation of Photonic Silicon Structures

The selectivity of the reactive ion etching of silicon using a negative electron resist AR-N 7520 mask was investigated. The selectivity dependencies on the fraction of SF6 in the feeding gas and bias voltage were obtained. To understand the kinetics of passivation film formation and etching, the type and concentration of neutral particles were evaluated and identified using plasma optical emission spectroscopy. Electron temperature and electron density were measured by the Langmuir probe method to interpret the optical emission spectroscopy data. A high etching selectivity of 8.0 ± 1.8 was obtained for the etching process. The optimum electron beam exposure dose for defining the mask was 8200 pC/m at 30 keV.

Dry etch performance of Novolak-based negative e-beam resist

Electron beam lithography (EBL) is pivotal for micro- and nanoscale fabrication, offering sub-micron precision. This study explores the utilization of the Novolac-based negative resist AR-N 7520 for EBL and its potential as an etch mask for reactive ion etching (RIE) of silicon. Recent comparisons of negative EBL resists have revealed promising results for AR-N 7520 in terms of resolution and adaptability with other lithography techniques. In this article, we conduct an exploration of patterning of AR-N 7520 (new) for EBL, addressing key parameters in achieving optimal patterning fidelity. Furthermore, we investigate its compatibility with RIE processes, aiming to provide insights into its effectiveness as an etch mask for creating sub-micron silicon structures. Experimental results show that optimal e-beam dose with 100 kV exposure is 300–350 μC/cm2. Selectivity of around 9:1 can be achieved by optimizing etching parameters for a continuous etch and higher than 14:1 for a cyclic etch process.

Characterization of the anti-reflectance laser-assisted etched silicon micro-nano structure for solar cell application

Characterization of the anti-reflectance laser-assisted etched silicon micro-nano structure for solar cell application

Novel and Low-Cost Techniques for Extending the Etch Capabilities of an Inductively Coupled Plasma Etch Tool That Has Clamp Fingers for Clamping 4-Inch Diameter Wafers

Widening the processing capabilities of an inductively coupled plasma (ICP) etch tool by “preventing wafer breakage” during processing of wafers, or by gaining the capability to do “through-wafer silicon etch” are important challenges that may need to be resolved with very limited resources. Resolving the undesired wafer breakage issues caused during processing of wafers is important to reduce the manufacturing costs, and increase production yield. Furthermore, considering the high prices of the state-of-the-art wafer processing tools, it is also important to prevent wafer breakage by using low-cost approaches especially if the resources for purchasing state-of-the-art processing equipment are not available. Two novel methods (method #1, and method #2) are developed to prevent wafer breakage and allow through-wafer silicon etching. With method #1, an aluminium alloy ring (AAR) and an o-ring are employed to obtain uniform load distribution (instead of point loads) on the required outer region on the surface of a wafer, and to minimize or completely remove the bending moment that may be formed on the possible cross-sections of the entire wafer, during clamping of the wafer. With method #2, through-wafer silicon etching is made possible by simultaneous application of method #1 and addition of a helium cooling gas (HCG) leakage blocking dicing tape at the back side of the wafer that is under processing for through-wafer etching. By using the explained methods, wafer breakage during ICP etch processing is eliminated, and through-wafer silicon etching is made possible. From the other side, the effective wafer area that can be used for processing is reduced by 48%. Novel and capability enabling 2 different techniques that are extremely low-cost compared to purchasing a state-of-the-art ICP etch tool are presented to extend the processing capabilities of an ICP etch tool for deep silicon etching (method #1), and through-wafer silicon etching (method #2).

Tuning surface reflectance and carrier lifetime of cone-shaped macropore structures obtained by platinum-assisted chemical etching of silicon

Tuning surface reflectance and carrier lifetime of cone-shaped macropore structures obtained by platinum-assisted chemical etching of silicon

Rapid graphene oxide assisted chemical etching of silicon in HF/H2O2 solution

In recent years, graphene oxide assisted etching silicon has been considered a potential method to replace metal-assisted chemical etching. This work demonstrated the catalytic ability of graphene oxide synthesized by the Hummers method to promote chemical etching of silicon. By adjusting HF/H2O2 ratio of the solution and reaction temperature, a minimum weighted average reflectance of 9.9% in the wavelength range of 300–1100 nm was obtained. An etching rate of 10 μm h−1, faster than those in others’ reports, was obtained in an optimized acidic solution at 80 °C. Finally, a four-electron model for graphene oxide assisted etching mechanism was proposed to explain our research results.

A transient site balance model for atomic layer etching

We present a transient site balance model of plasma-assisted atomic layer etching of silicon (Si) with alternating exposure to chlorine gas (Cl2) and argon ions (Ar+). Molecular dynamics (MD) simulation results are used to provide parameters for the model. The model couples the dynamics of a top monolayer surface region (‘top layer’) and a perfectly mixed subsurface region (‘mixed layer’). The differential equations describing the rates of change of the Cl coverage in the two layers are transient mass balances. Model predictions include Cl coverages and rates of etching of various species from the surface as a function of Cl2 or Ar+ fluence. The simplified phenomenological model reproduces the MD simulation results well over a range of conditions. Comparing model predictions directly to experimental optical emission spectroscopy data, as reported in a previous paper (Vella et al 2023 J. Vac. Sci. Technol. A 41, 062602), provides further evidence of the accuracy of the model.

In Ukrainian

The paper describes the method of obtaining the SiC/porous-Si/Si heterostructure and the study of its structural and morphological properties. The method of obtaining heterostructures consisted of several stages: electrochemical etching of single-crystal silicon p-Si (111), annealing of porous Si in a CO atmosphere. The fabricated structures were characterized using scanning electron microscopy, X-ray spectral microanalysis, X-ray phase analysis, high-resolution diffractometry, X-ray reflectometry, and photoluminescence. The method of high-resolution diffractometry made it possible to assess the state of the SiC/Si(001) system. On the 2Theta-omega diffractograms, in addition to the (111) reflection of the Si substrate in the region of 2 Theta = 35.67, the (111) reflection of the cubic SiC film is observed. This means that the formed SiC film is textured in the (111) growth direction of the silicon substrate. The classical technique of X-ray phase analysis showed the presence of a hexagonal phase in the SiC film. The concentration ratio of cubic to hexagonal phase is 80 % cubic and 20 % hexagonal. The RMS deformation of the lattice (ε) in such a structure is ε = 1∙10–2. The photoluminescence spectra of the SiC films of the experimental samples in most cases consist of narrow and broad bands and extend from the near ultraviolet to the entire visible spectrum. At the same time, in the range of wavelengths corresponding to the energy forbidden zones of hexagonal polytypes and cubic polytypes, a noticeable glow was observed in most of the samples. In some samples, luminescence in the area of hexagonal phases was predominant. In the photoluminescence spectra both at T = 77 K and at T = 300 K, a narrow line at a wavelength of ~ 371 nm is observed.

Cryogenic DRIE processes for high-precision silicon etching in MEMS applications

Cryogenic deep reactive ion etching (Cryo DRIE) of silicon has become an enticing but challenging process utilized in front-end fabrication for the semiconductor industry. This method, compared to the Bosch process, yields vertical etch profiles with smoother sidewalls not subjected to scalloping, which are desired for many microelectromechanical systems (MEMS) applications. Smoother sidewalls enhance electrical contact by ensuring more conformal and uniform sidewall coverage, thereby increasing the effective contact area without altering contact dimensions. The versatility of the Cryo DRIE process allows for customization of the etch profiles by adjusting key process parameters such as table temperature, O2 percentage of the total gas flow rate (O2 + SF6), RF bias power and process pressure. In this work, we undertake a comprehensive study of the effects of Cryo DRIE process parameters on the trench profiles in the structures used to define cantilevers in MEMS devices. Experiments were performed with an Oxford PlasmaPro 100 Estrelas ICP-RIE system using positive photoresist SPR-955 as a mask material. Our findings demonstrate significant influences on the sidewall angle, etch rate and trench shape due to these parameter modifications. Varying the table temperature between −80 °C and −120 °C under a constant process pressure of 10 mTorr changes the etch rate from 3 to 4 μm min−1, while sidewall angle changes by ∼2°, from positive (<90° relative to the Si surface) to negative (>90° relative to the Si surface) tapering. Altering the O2 flow rate with constant SF6 flow results in a notable 10° shift in sidewall tapering. Furthermore, SPR-955 photoresist masks provide selectivity of 46:1 with respect to Si and facilitates the fabrication of MEMS devices with precise dimension control ranging from 1 to 100 μm for etching depths up to 42 μm using Cryo DRIE. Understanding the influence of each parameter is crucial for optimizing MEMS device fabrication.

A High-Aspect-Ratio Deterministic Lateral Displacement Array for High-Throughput Fractionation.

Future industrial applications of microparticle fractionation with deterministic lateral displacement (DLD) devices are hindered by exceedingly low throughput rates. To enable the necessary high-volume flows, high flow velocities as well as high aspect ratios in DLD devices have to be investigated. However, no experimental studies have yet been conducted on the fractionation of bi-disperse suspensions containing particles below 10 µm with DLD at a Reynolds number (Re) above 60. Furthermore, devices with an aspect ratio of more than 4:1, which require advanced microfabrication, are not known in the DLD literature. Therefore, we developed a suitable process with deep reactive ion etching of silicon and anodic bonding of a glass lid to create pressure-resistant arrays. With a depth of 120 µm and a gap of 23 µm between posts, a high aspect ratio of 6:1 was realized, and devices were investigated using simulations and fractionation experiments. With the two-segmented array of 3° and 7° row shifts, critical diameters of 8 µm and 12 µm were calculated for low Re conditions, but it was already known that vortices behind the posts can shift these values to lower critical diameters. Suspensions with polystyrene particles in different combinations were injected with an overall flow rate of up to 15 mL/min, corresponding to Re values of up to 90. Suspensions containing particle combinations of 2 µm with 10 µm as well as 5 µm with 10 µm were successfully fractionated, even at the highest flow rate. Under these conditions, a slight widening of the displacement position was observed, but there was no further reduction in the critical size as it was for Re = 60. With an unprecedented fractionation throughput of nearly 1 L per hour, entirely new applications are being developed for chemical, pharmaceutical, and recycling technologies.

Controlled fabrication of upright and inverted pyramid arrays of silicon via the interaction of copper ions and oxidants in hydrofluoric acid

Recent advances in chemical etching of silicon have allowed its widespread use in the fabrication of microelectronic devices and energy converters, in which shaped silicon exhibits outstanding properties and functions. The texturing process used to fabricate light-trapping structures on silicon surfaces is an indispensable step in preparing solar cells. Here, this manuscript describes the use of a one-step wet chemical etching method with copper as a catalyst to manufacture different structures, including inverted pyramid structures and upright pyramid structures, on silicon surfaces, which can be easily controlled by varying the solution composition and etching time. Moreover, this manuscript demonstrates an exciting method for fabricating random inverted pyramid and random upright pyramid arrays of silicon. The findings provide important contributions that can help improve the fabrication methods for silicon-based solar cell devices and optimize the light trapping structure on the cell surface.

PLASMA PARAMETRS AND SILICON ETCHING KINETICS IN CF4 + C4F8 + O2 MIXTURE: EFFECT OF CF4/C4F8 MIXING RATIO

In this work, we investigated the influence of fluorocarbon component ratio in the CF4 + C4F8 + O2 gas mixture on electro-physical plasma parameters, steady-state densities of active species and silicon etching kinetics under typical reactive-ion process conditions. The combination of plasma diagnostics (double Langmuir probes, optical emission spectroscopy) and plasma modeling confirmed known peculiarities of plasma chemistry of individual fluorocarbons in the presence of oxygen as well as provided an extended analysis of both fluorine and oxygen atom kinetics in the three-component gas mixture. It was shown that the substitution of CF4 by C4F8 at the constant fraction of O2 a) causes the weak disturbance in electrons- and ions-related plasma parameters (electron temperature, electron density, ion energy flux); b) provides drastically increasing density of polymerizing CFx (x = 1, 2) radicals; and c) results in monotonically decreasing F atoms density. The latter is due to simultaneous changes in both F atom formation rate and their loss frequency, especially in C4F8-rich plasmas. From experiments, it was found that Si etching rate is by more than 85% controlled by its chemical component (in a form of ion-stimulated heterogeneous reaction Si + xF → SiFx) and decreases with increasing C4F8 fraction in a feed gas. The change in effective reaction probability contradicts with the growth of polymer deposition rate and film thickness (as it follows from changes in gas-phase plasma characteristics) but may reflect the weakening of surface passivation by oxygen atoms. For citation: Efremov A.M., Bobylev A.V., Kwon K.-H. Plasma parametrs and silicon etching kinetics in CF4 + C4F8 + O2 mixture: effect of CF4/C4F8 mixing ratio. ChemChemTech [Izv. Vyssh. Uchebn. Zaved. Khim. Khim. Tekhnol.]. 2024. V. 67. N 6. P. 29-37. DOI: 10.6060/ivkkt.20246706.6982.

Wet Etching of Silicon in Planar Nanochannels.

Silicon (Si) alkaline etching constitutes a fundamental process in the semiconductor industry. Although its etching kinetics on plain substrates have been thoroughly investigated, the kinetics of Si wet etching in nanoconfinements have yet to be fully explored despite its practical importance in three-dimensional (3-D) semiconductor manufacturing. Herein, we report the systematic study of potassium hydroxide (KOH) wet etching kinetics of amorphous silicon (a-Si)-filled two-dimensional (2-D) planar nanochannels. Our findings reveal that the etching rate would increase with the increase in nanochannel height before reaching a plateau, indicating a strong nonlinear confinement effect. Through investigation using etching solutions with different ionic strengths and/or different temperatures, we further find that both electrostatic interactions and the hydration layer inside the nanoconfinement contribute to the confinement-dependent etching kinetics. Our results offer fresh perspectives into the kinetic study of reactions in nanoconfinements and will shed light on the optimization of etching processes in the semiconductor industry.