Estimates Of Speedup Research Articles

A fast parallelized DBSCAN algorithm based on OpenMp for detection of criminals on streaming services.

Streaming services are highly popular today. Millions of people watch live streams or videos and listen to music. One of the most popular streaming platforms is Twitch, and data from this type of service can be a good example for applying the parallel DBSCAN algorithm proposed in this paper. Unlike the classical approach to neighbor search, the proposed one avoids redundancy, i.e., the repetition of the same calculations. At the same time, this algorithm is based on the classical DBSCAN method with a full search for all neighbors, parallelization by subtasks, and OpenMP parallel computing technology. In this work, without reducing the accuracy, we managed to speed up the solution based on the DBSCAN algorithm when analyzing medium-sized data. As a result, the acceleration rate tends to the number of cores of a multicore computer system and the efficiency to one. Before conducting numerical experiments, theoretical estimates of speed-up and efficiency were obtained, and they aligned with the results obtained, confirming their validity. The quality of the performed clustering was verified using the silhouette value. All experiments were conducted using different percentages of medium-sized datasets. The prospects of applying the proposed algorithm can be obtained in various fields such as advertising, marketing, cybersecurity, and sociology. It is worth mentioning that datasets of this kind are often used for detecting fraud on the Internet, making an algorithm capable of considering all neighbors a useful tool for such research.

Parallel methods and algorithms for solving problems of digital filtering of data arrays

A quasisystolic computation method for solving digital filtering problems of various dimensions on specialized computing means – quasisystolic structures is proposed. This method makes it possible to build parallel-pipeline computation algorithms that are optimal in speed and memory usage. Based on the ideas of the pyramid method for parallelization of cycles, parallel algorithms with autonomous branches were built for solving filtering problems on clusters, hybrid architectures and computers with a multi-core processor. Theoretical speed-up estimates were obtained, which confirm the high efficiency of the constructed parallel filtering algorithms. For individual algorithms with autonomous branches, real speed-up estimates were obtained, which are in good agreement with the theoretical ones. The obtained results can be used for preliminary processing of large arrays of input data in various subject areas

Scalable Local Timestepping on Octree Grids

Numerical solutions of hyperbolic partial differential equations (PDEs) are ubiquitous in science and engineering. Method of lines is a popular approach to discretize PDEs defined in spacetime, where space and time are discretized independently. When using explicit timesteppers on adaptive grids, the use of a global timestep size dictated by the finest grid-spacing leads to inefficiencies in the coarser regions. Even though adaptive space discretizations are widely used in computational sciences, temporal adaptivity is less common due to its sophisticated nature. This paper presents highly scalable algorithms to enable local timestepping (LTS) for explicit timestepping schemes on octrees. We demonstrate the accuracy of our methods and the scalability of our framework across 16K cores on TACC's Frontera supercomputer https://frontera-portal.tacc.utexas.edu/. We also present a speedup estimation model for LTS that predicts the distributed speedup compared to global timestepping with an average of 0.1 relative error.

Neural Network in Keystroke Dynamics in Biometric Authentication System

Abstract: In the proposed approach writing speed can be improved by low over head techniques for screening key designs. It is fast and different ways are used to integrate to existing conventions. A more expensive scope of client is allowed to test for equivalent overhead. Proposed method potential predispositions are responsible, so they can be measured and balanced. The comparator has been used a existing standard layout. Mapping both layouts can eliminate differing familiarity and finger memory bias. Delineate it with two cell phone keypad formats: Sam-sung's variation of the basic ABC design, and another client particular design (PM). We rehash an examination beforehand attempted by a preparation based technique, which utilized 10 members, and evaluated a 54% speedup for PM (SD=35%). The new strategy utilized 116 members and assessed a 19.5% speedup (SD=7.5%). Wide confidence interval of the training-based methods, differences in test corpuses, and the inherent conservatism of the new method which is used to explain the Differences in speedup estimates. As a result of large test group the effects of user uniqueness tested significantly. There is no obvious effect on any of the measures. ABC and PM performance were significantly related age and keypad experience. Age and Keypad experience does not affect the relative speed. A different experience level of comparison bias has been removed by proposed approach. Keywords: ABC design, PM performance, Neural Network

Sequential fully implicit Newton method for compositional flow and transport

Compositional simulation for flow and transport in porous media is essential for modeling Enhanced Oil Recovery (EOR) processes. The Sequential Fully Implicit (SFI) scheme is considered as a more flexible and potentially more computationally efficient alternative to the commonly used Fully Implicit Method (FIM). SFI was proposed along with the multiscale method where the flow and transport problems are solved in sequence. SFI opens the door for flexible discretizations, specialized linear solvers, and adaptive strategies. In the SFI method, a time step entails several ‘outer’ iterations. Each iteration consists of two steps: (1) a pressure equation is formed and solved implicitly, and then (2) a set of transport equations is solved, also implicitly. The (outer) iterations are conducted in a fixed-point manner until global convergence is reached. SFI can suffer from slow convergence, or even convergence failure, in strongly coupled flow and transport problems. Examples include dominant buoyancy and complex phase behaviors which are typical in compositional processes. Wong et al. [40] proposed the Sequential Fully Implicit Newton (SFIN) method for multi-physics problems in reservoir simulation and achieved superior outer loop convergence. In this work, we develop the SFIN method for compositional flow and transport problems, and in particular, show how the main assumption of fixing the total velocity can be incorporated. The key step of the SFIN method is a global Newton update that is performed at the end of each flow-transport iteration. During this outer Newton step, the pressure and transport variables are updated together to resolve the coupling between them better. The corresponding linear system is solved by a Krylov solver (e.g., GMRES) using a Jacobian-free approach that only entails matrix-vector multiplications. The latter is constructed by reusing previously computed Jacobian matrices and their preconditioners' information in a computationally efficient way. We present several challenging two- and three-dimensional examples and show that the SFIN method can significantly reduce the number of outer and inner loop iterations compared with the original (non-accelerated) SFI method. We analyze both the nonlinear and linear convergence behaviors for the SFIN method's key components and provide potential speedup estimates with respect to the SFI method.

Parallel Solutions of Parametric Problems in Gas Dynamics Using DVM/DVMH Technology

This paper investigates the effectiveness of the DVM/DVMH technology as applied to the parallel solution of parametric problems in gas dynamics. The solution of these problems is based on the construction of a generalized computational experiment, which involves multiple solutions of the problem with the variation of its key parameters. This approach is efficient only when using parallel technologies, which make it possible to organize the concurrent solution of the problem with various input data in multitasking mode. We conducted a series of numerical experiments to solve one-dimensional and two-dimensional parametric problems of gas dynamics by varying the number of computational nodes, their parameters, and graphics coprocessors connected. The computational results for these test problems in the form of efficiency and speedup estimates are presented.

Estimation of Maximum Speed-Up in Multicore-Based Mobile Devices

This letter proposes an effective speed-up estimation method for modern mobile devices. Unlike existing approaches, the proposed method uses a task graph to extract multiple parallelizable fractions of real-world mobile scenarios. Then, it uses the extracted parallelizable fractions to estimate the theoretical maximum speed-up of mobile devices. In experiments, the proposed method estimated the maximum speed-up of mobile devices more accurately than the state-of-the-art speed-up estimation method.

Performance Estimation of Task Graphs Based on Path Profiling

Correctly estimating the speed-up of a parallel embedded application is crucial to efficiently compare different parallelization techniques, task graph transformations or mapping and scheduling solutions. Unfortunately, especially in case of control-dominated applications, task correlations may heavily affect the execution time of the solutions and usually this is not properly taken into account during performance analysis. We propose a methodology that combines a single profiling of the initial sequential specification with different decisions in terms of partitioning, mapping, and scheduling in order to better estimate the actual speed-up of these solutions. We validated our approach on a multi-processor simulation platform: experimental results show that our methodology, effectively identifying the correlations among tasks, significantly outperforms existing approaches for speed-up estimation. Indeed, we obtained an absolute error less than 5 % in average, even when compiling the code with different optimization levels.

A Rapid Screening and Testing Protocol for Keyboard Layout Speed Comparison

We propose an efficient low-overhead methodology for screening key layouts for ultimate typing speed. It is fast and complementary to existing protocols in other ways. For equal overhead, it allows testing over a wider range of users. It is subject to potential biases, but they can be quantified and adjusted. It assumes an existing standard layout which is used as a comparator. It eliminates bias from differing familiarity and finger memory by appropriately mapping both layouts. We illustrate it with two mobile phone keypad layouts: Samsung's variant of the common ABC layout, and a new user-specific layout (PM). We repeat a comparison previously undertaken by a training-based method, which used ten participants, and estimated a $54\%$ speedup for PM (SD = $35\%$ ). The new method used 116 participants and estimated a $19.5\%$ speedup (SD = $7.5\%$ ). Differences in speedup estimates can be explained by the wide confidence interval of the training-based methods, differences in test corpuses, and the inherent conservatism of the new method. Effects of user characteristics could be meaningfully tested due to the larger test group. Gender had no detectable effect on any of the measures, but age and keypad experience were significantly related to ABC and PM performance. However, the relative speedup was unaffected by age or keypad experience: the method can remove comparison biases arising from differing experience levels.

Use of supercomputer for modeling coherent processes in magnetic nano-structures

Abstract Multi-scale spin dynamics of systems of nanomagnets is investigated by numerical simulation using parallel algorithms. A FORTRAN program was developed using an application programming interface OpenMP. The parallel code provides following areas of research: study of the possibility of regulation time of switching of magnetization of the nanostructure; study of the role of nanocrystal geometry of coherent relaxation of 1-, 2- and 3-dimensional objects; study of magnetodynamics of spin system coupled with the passive resonator (radiation damping (RD)); application of RD to ultra-fast relaxation in an assembly of single-domain ferromagnetic particles; study of the role of long distant dipole–dipole fields as the origin of the extremely random behavior in hyperpolarized NMR maser, etc. Estimates of speedup and efficiency of implemented algorithms in comparison with sequential algorithms have been obtained. It is shown that the use of supercomputing technology for study of spin dynamics provides simulation power for spin systems which include thousands of magnetic voxels.

Особливості конструкції одноцокольних ламп для ультрафіолетового опромінювання

The construction of bactericidal lamp with one cap for ultraviolet irradiation is offered in the article. The investigations of low-pressure lamp lifetime in the mode of speed-up estimation and in the mode of annealing with the use of different electric charts of feed are conducted. The factors that influence on the parameters of investigational lamps are determined.

Kismet

Software engineers now face the difficult task of refactoring serial programs for parallel execution on multicore processors. Currently, they are offered little guidance as to how much benefit may come from this task, or how close they are to the best possible parallelization. This paper presents Kismet, a tool that creates parallel speedup estimates for unparallelized serial programs. Kismet differs from previous approaches in that it does not require any manual analysis or modification of the program. This difference allows quick analysis of many programs, avoiding wasted engineering effort on those that are fundamentally limited. To accomplish this task, Kismet builds upon the hierarchical critical path analysis (HCPA) technique, a recently developed dynamic analysis that localizes parallelism to each of the potentially nested regions in the target program. It then uses a parallel execution time model to compute an approximate upper bound for performance, modeling constraints that stem from both hardware parameters and internal program structure. Our evaluation applies Kismet to eight high-parallelism NAS Parallel Benchmarks running on a 32-core AMD multicore system, five low-parallelism SpecInt benchmarks, and six medium-parallelism benchmarks running on the finegrained MIT Raw processor. The results are compelling. Kismet is able to significantly improve the accuracy of parallel speedup estimates relative to prior work based on critical path analysis.

Speedup estimates for some variants of the parallel implementations of the branch-and-bound method

The efficiency of parallel implementations of the branch-and-bound method in discrete optimization problems is considered. A theoretical analysis and comparison of two parallel implementations of this method is performed. A mathematical model of the computation process is constructed and used to obtain estimates of the maximum possible speedup. Examples of problems in which none of these two parallel implementations can speed up the computations are considered.

A Parallel Simulation Methodology for Speedup and Obtaining Performance Estimates with Specific Accuracy: Experiences of its Application in Studies of Metropolitan Area Networks

Performance measures obtained by stochastic simula tion are estimates, and one must consider the precision of the estimates before making any constructive con clusions about the investigated systems. This paper applies an automated distributed simulation method, called Spectral Analysis in Parallel Time Streams, to speed up production of performance estimates, and for run-length determination in the simulation of High- speed Metropolitan Area Networks (MANs). This method makes sequential simulators suitable for par allel execution on multiprocessors and/or networked computers. At runtime it estimates the information content of observations generated during simulation, generates a point estimate and confidence interval, and directs the run to continue until an estimate is obtained that achieves or exceeds our required level of precision. The application of this methodology for studying high-speed MANs, the speedup, intermachine communication and "warm-up" overhead, and the run lengths needed to produce estimates with a specific level of precision, are reported for each of the param eters investigated. Practical implications are discussed.

Prototyping of Tightly Coupled Hardware/Software-Systems

Verification and test issues raise the need for rapid prototyping of complex systems and especially hardware/software-systems. We tackle this problem by integration of hardware/software-codesign and prototyping. First we define the concept of the entire system architecture. This concept directs the hardware/software-partitioning process. Our prototyping environment reflects the architecture concept as well. In this overview the architecture concept and all important design tasks (hardware/software-partitioning, speed-up estimation before HW-synthesis, and prototyping of the entire hardware/software-system) are presented and compared to several approaches from literature. Thus a substantial overview over the prototyping problem is given. The latter part of this presentation illustrates our approach by a case study and presents the results. Our automated design process generates a tightly coupled hardware/software-system with very good performance characteristics. The case study focus on the prototyping of a ciphering algorithm. The reported approach leads to a reasonable overall system speed-up of 10 percent. Similar results have been found for further examples as well.

Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources

This paper presents a new approach for improving the efficiency of large VLSI parallel systems called the Dynamic Concatenation Approach (DCA). The basic idea of DCA is to concatenate bit-serial processing elements to construct bit-parallel processors of variable width. The concatenation permits an increase in the storage capacity of each processor which can be used to keep a number of local variables within the processor registers. A model for evaluating the performance speed-ups that could be achieved using DCA is developed. Arbitrary architectural characteristics as well as program characteristics are both taken into account in this model. Speed-up estimates are obtained by considering the effect of DCA when the variables of three programs are allocated to the registers of the processing elements. It is shown that DCA significantly improves performance in systems where I/O bottlenecks exist.

A tridiagonal system solver for distributed memory parallel processors with vector nodes

A variant of the odd-even cyclic reduction algorithm for solving tridiagonal linear systems is presented. Of particular interest is the case where the number of equations is much larger than the number of processors. The target architecture for this scheme is a distributed-memory parallel computer with nodes which are vector processors. The partitioning of the matrix system is governed by a parameter which determines the amount of redundancy in computations and the amount of communication. One feature of the method is that computations are well balanced, as each processor executes an identical algebraic routine. A brief description of the standard cyclic reduction algorithm is given. Then a divide and conquer strategy is presented along with some estimates of speedup and efficiency. Finally, FORTRAN programs for this algorithm which run on the Intel iPSC/2-VX and Floating Point Systems FPS T-20 computer are discussed along with experimental results. Of particular interest is the performance evaluation of this algorithm according to Gustafson's concept of scaled speedup.

Concurrency enhancement through program unification: A performance analysis

A novel unification scheme was proposed that constructs an N-dimensional transformation of a given program such that a single execution of the transformed program effectively substitutes for a serial execution of the original program on N different data sets. Our studies show that the speedup thus obtained makes the scheme a very attractive alternative in situations where a given program P is required to be executed on several data sets simultaneously. This is true, in particular, when the original program P does not lend itself well to vectorization or concurrentization. In order to obtain an understanding of the operation of the transformed program, we construct stochastic urn models of program execution for small configurations. By comparing the execution times for the urn model counterparts of the original program P and its transformation, we obtain estimates of speedup given by the transformation. While the models that we present are computationally exact, they typically possess large state spaces for realistic values of model parameters. In such instances, we build simulated versions of the urn models, use the analytic models to validate our simulation models, and use the latter models for combinations of system parameters that make the state space large.

An accurate and efficient performance analysis technique for multiprocessor snooping cache-consistency protocols

A number of dynamic cache consistency protocols have been developed for multiprocessors having a shared bus interconnect between processors and shared memory. The relative performance of these protocols has been studied extensively using simulation and detailed analytical models based on Markov chain techniques. Both of these approaches use relatively detailed models, which capture cache and bus interference rather precisely, but which are highly expensive to evaluate. In this paper, we investigate the use of a more abstract and significantly more efficient analytical model for evaluating the relative performance of cache consistency protocols. The model includes bus interference, cache interference, and main memory interference, but represents the interactions between the caches by steady-state mean collision rates which are computed by iterative solution of the model equations. We show that the speedup estimates obtained from the mean-value model are highly accurate. The results agree with the speedup estimates of the detailed analytical models to within 3%, over all modifications studied and over a wide range of parameter values. This result is surprising, given that the distinctions among the protocols are quite subtle. The validation experiments include sets of reasonable values of the workload parameters, as well as sets of unrealistic values for which one might expect the mean-value equations to break down. The conclusion we can draw is that this modeling technique shows promise for evaluating architectural tradeoffs at a much more detailed level than was previously thought possible. We also discuss the relationship between results of the analytical models and the results of independent evaluations of the protocols using simulation.