ESD-induced Noise Research Articles

Field source extraction of an ESD generator and its application to system-level ESD analysis in a solid-state storage system

System-level electrostatic discharge (ESD) noise due to electromagnetic fields radiating from an ESD generator were measured and analyzed in a solid-state drive (SSD) storage system. The field sources of an ESD generator were efficiently modeled from the measured tangential magnetic fields in front of a ESD generator. The extracted field sources were incorporated into a full-wave solver, and the fields inside the disk-array enclosure (DAE) were simulated and validated by comparing to measured fields. The field source models of the ESD generator were then also utilized to predict transient ESD-induced noise voltages in a simplified SSD. Finally, the coupling mechanism and the effects of the DAE geometry were investigated.

A Cost-Effective Structure for Secondary Discharge Control to Improve System-Level ESD Immunity of a Mobile Product

A structure embedded in a printed circuit board is proposed to control secondary discharge currents and improve the system-level electrostatic discharge (ESD) immunity for a mobile product with a metal frame. Noise voltages and discharge currents were measured and analyzed according to several secondary discharge paths, such as an air arc, a voltage suppressor device, and with the interlaced suppression device. ESD events that caused soft failures of a real commercial mobile product were tested while a high-definition video was playing. System-level ESD-induced noise and soft failures were cost effectively reduced by the interlaced suppression device.

ESD-Induced Noise to Low Noise Amplifier Circuits in BiCMOS

Electrostatic discharge (ESD) induced parasitic effects have serious impacts on performance of radio frequency (RF) integrated circuits (IC). This paper discusses a comprehensive noise analysis procedure for ESD protection structures and their negative influences on RF ICs. Noise figures (NFs) of commonly used ESD protection structures and their impacts on a single-chip 5.5 GHz low-noise amplifier (LNA) circuit were depicted. A design example in 0.18 μm SiGe BiCMOS was presented. Measurement results confirm that significant noise degradation occurs in the LNA circuit due to ESD-induced noise effects. A practical design procedure for ESD-protected RF ICs is provided for real-world RF IC optimization.