Error Tolerance Capability Research Articles

Non-volatile flip-flop with soft error tolerant capability using DICE and C-element

Non-volatile flip-flop with soft error tolerant capability using DICE and C-element

Novel variable precision fuzzy rough sets and three-way decision model with three strategies

Variable precision (fuzzy) rough sets are interesting generalizations of Pawlak rough sets and can handle uncertain and imprecise information well due to their error tolerance capability. The comparable property (CP for short), i.e., the lower approximation is included in the upper approximation, is fundamental in Pawlak rough sets since many theories and applications rely on this property. However, the CP is lost in many existing variable precision (fuzzy) rough sets. Therefore, a novel variable precision fuzzy rough set model with CP is proposed and an associated three-way decision model is developed. Firstly, a pair of variable precision fuzzy upper and lower approximation operators are defined and studied through fuzzy implication and co-implication operators. We show that this pair of approximation operators satisfy various properties (including CP) that the existing variable precision fuzzy approximation operators do not possess. Secondly, new methods for constructing loss functions and conditional probabilities are given by using CP, and then a new three-way decision model with three strategies (optimistic, pessimistic, and compromise strategies) is established. Finally, an explanatory example is provided to examine validity, stability and sensitivity of the proposed three-way decision model.

Accurate Storm Surge Prediction with a Parametric Cyclone and Neural Network Hybrid Model

Storm surges are one of the most devastating coastal disasters. Numerous efforts have continuously been made to achieve better prediction of storm surge variation. In this paper, we propose a parametric cyclone and neural network hybrid model for accurate, long lead-time storm surge prediction. The model was applied to the northeastern coastal region of Taiwan, i.e., Longdong station. A total of 14 historical typhoon events were used for model training and validation, and the results and questions associated with this hybrid approach carefully discussed. Overall, the proposed method reduced the complexity of network structure while retaining the important typhoon indicators. In particular, local pressure and winds estimated from the storm parameters through physically-based parametric cyclone models allow for inferring the possible future influence of a typhoon, unlike the simple collection and direct usage of observation data from local stations in earlier works. Meanwhile, the error-tolerance capability of the neural network alleviated some discrepancy in the model inputs and enabled good surge prediction. Further, the proposed method showed better and faster convergence thanks to the retention of storm information and the reduced dimensions of the search space. The hybrid model presented excellent performance or maintained reasonable capability for short lead-time and long lead-time storm surge prediction. Compared with the pure neural network model under the same network dimensions, the present model demonstrated great improvement in accuracy as the prediction lead time increased to 8 h, e.g., 33–40% (13–21%) and 32–37% (18–29%) RMSE and CE, respectively, in the training/validation phase.

High error-tolerable unit protection for VSC-MTDC independent of data synchronization

Unit protection is a promising technique to enable full coverage for DC lines in the VSC-based Multiterminal DC (VSC-MTDC) grid. However, this type of protection element usually performs as a back-up one, mainly due to its limited speed and error-tolerance capability. To solve this problem, a novel type of unit protection is proposed in this paper. Based on the profile of initial surge arrival, this paper uses the Hausdorff Distance (HD) to measure the similarity between the initial backward/forward surges in a short time-window, which distinguishes internal faults from external ones, eliminating the need for data synchronization. To enhance high error-tolerance capability, an adaptive median filtering-based approach is proposed to reduce the impact of abnormal voltage spikes and white noise, while maintaining the similarity profile of the initial backward/forward surges for the calculation of HD. Simulation results demonstrate that the proposed protection method is capable of identifying internal faults before the blocking of the Half-bridge MMC converter, and the resistive coverage is 300 Ohm in most cases. Under the external fault condition, the proposed protection can be secure enough even in the challenging scenario of white noises and abnormal spikes considered.

A biologically plausible network model for pattern storage and recall inspired by Dentate Gyrus

In the race to achieve better performance, artificial intelligence has become more about the end rather than the means, which is general intelligence. This work aims to bridge the gap between the two by finding a complementary midline. The objective of this work is to project the role of Dentate Gyrus in enhancing the performance of an autoassociative network, paving the way to develop a biologically plausible neural network which, in the future, would help in simulating the network present in our brain. The proposed network imbibes biological similarities with respect to connectivity, weight updation, and activation function. Dentate Gyrus uses pre-integration lateral inhibition form of learning, and the autoassociative network is implemented using Hopfield network. The performance of the autoassociative network in the presence and absence of Dentate Gyrus is observed across multiple parameters. The results show an increase of 38% in storage capacity and a decrease of 15% in the error tolerance capability of the network in the presence of Dentate Gyrus.

Low power and area efficient error tolerant adder for image processing application

SummaryApproximate computing‐based arithmetic units are oriented towards reduction in power, delay, and area. Intrinsic error tolerance capability of emerging application domains, like multimedia, Internet of Things (IoT), and image processing provides better opportunities for optimization of approximate arithmetic units. In this paper, a novel 1‐bit imprecise full adder (IFA) is proposed with less gate count. Also, two versions of 16‐bit error tolerant adders (ETAs), namely a low power and area efficient error tolerant adder (LETA) and improved low power and area efficient error tolerant adder (ILETA), are proposed. In these proposed ETAs, the most significant bit (MSB) segments are realized in same approach, whereas the least significant bit (LSB) segment of LETA and ILETA are realized using an existing modified full adder (MFA) and proposed IFAs, respectively. The proposed and existing ETA adders are implemented using a Verilog hardware description language (HDL) and synthesized in a Synopsys electronic design automation (EDA) Tool using Taiwan Semiconductor Manufacturing Company (TSMC) 65nm technology. The proposed (ILETA, LETA) adders exhibit (55%, 50%) reduction in power consumption and achieve significant reduction in area (68%, 61%). Further, in this work, a new performance metric namely power and error product (PEP) is proposed in order to evaluate the approximate adders in terms of power and error metrics. It is found that the proposed ILETA achieves a low PEP of 1.05 compared with other ETAs. To study the efficacy of the proposed ETA adders in image processing application, an image blending algorithm is implemented and simulated using MATLAB. From simulation results, it is observed that the proposed ETA adders exhibit a high peak signal‐to‐noise ratio (PSNR).

Leakage Identification in Water Distribution Networks with Error Tolerance Capability

Leakages in water distribution networks have caused considerable waste of water resources. Thus, this study proposes a novel method for hydraulically monitoring and identifying regions where leakages occur in near-real time. A large network is first divided into several identification regions. To exploit a strong constructive and discriminative power, sparse coding is used, thereby adaptively coding the information embedded in observed pressures efficiently and succinctly. And a linear classifier is trained to determine the most likely leakage regions. A benchmark case is presented in this study to demonstrate the effectiveness of the proposed method. Results indicate that the proposed method can identify leakage events with enhanced tolerance capability for measurement errors. The method is also partially effective for identifying two simultaneous leakages. Certain practical advice in balancing the number of sensors and regions is also discussed to enhance the application potential of this method.

A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing

The massively parallel computing systems composed of many processors are connected on chips, which will become more and more complex and unreliable. This paper presents an error-tolerant design based on the autonomous error-tolerant (AET) architecture that aims to have a self-repairing capability. A nearby error sensing mechanism is designed to discover faults, and an active evolution scheme is studied to handle unrecoverable errors. A circuit backup switching mechanism is proposed to bypass the failed nodes. The board-level prototype is implemented based on dual-core embedded processors. The analysis shows that the error-tolerant capability of the proposed architecture is better than the conventional multimodular redundant system when the failure rate of a single core is less than 0.7. In the AET test system consisting of 16 processors, the error-tolerant capability is verified. The results show that the relative variation of the overall performance of the AET system will not be changed due to the high reliability requirements of the system. Through experimental comparison, under the premise that the architecture of AET and the triple modular redundancy method are basically consistent in reliability, whether on the logical-level error tolerant or on the physical-level error tolerant, the former has lower power consumption.

A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors

The aggressive scaling of semiconductor technology has significantly increased the radiation-induced soft-error rate in modern microprocessors. Meanwhile, due to the increasing complexity of modern processor pipelines and the limited error-tolerance capabilities that previous radiation hardening techniques can provide, the existing pipeline protection mechanisms cannot achieve complete protection. This paper proposes a complete and cost-effective pipeline protection mechanism using a self-checking architecture. The radiation-hardened pipeline is achieved by incorporating soft-error- and timing-error-tolerant flip-flop (SETTOFF)-based self-checking cells into the sequential cells of the pipeline. A replay recovery mechanism is also developed at the architectural level to recover the detected errors. The proposed pipeline protection technique is implemented in an OpenRISC microprocessor in a 65-nm technology. A gate-level transient fault-injection and analysis technique is used to evaluate the error-tolerance capability of the proposed hardened pipeline design. The results show that compared with the techniques such as triple modular redundancy, the SETTOFF-based self-checking technique requires over 30% less area and 80% less power overheads. Meanwhile, the error-tolerant and self-checking capabilities of the register allow the proposed pipeline protection technique to provide a noticeably higher level of reliability for different parts of the pipeline compared with the previous pipeline protection techniques.

SET and noise fault tolerant circuit design techniques: Application to 7 nm FinFET

In the near future of high component density and low-power technologies, soft errors occurring not only in memory systems and latches but also in the combinational parts of logic circuits will seriously affect the reliable operation of integrated circuits. This paper presents a novel design style which reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments. The independent design style of this method achieves SET mitigation and noise immunity by strengthening the sensitive nodes using a technique similar to feedback. A realization for this methodology is presented in 7nm FinFET and in order to check the accuracy of our proposal, we compare it with others techniques for hardening radiation at the transistor level against a single event transient. Simulation results show that the proposed method has a good soft error tolerance capability as well as better noise immunity.

High-Rate Self-Synchronizing Codes

Self-synchronization under the presence of additive noise can be achieved by allocating a certain number of bits of each codeword as markers for synchronization. Difference systems of sets are combinatorial designs which specify the positions of synchronization markers in codewords in such a way that the resulting error-tolerant self-synchronizing codes may be realized as cosets of linear codes. Ideally, difference systems of sets should sacrifice as few bits as possible for a given code length, alphabet size, and error-tolerance capability. However, it seems difficult to attain optimality with respect to known bounds when the noise level is relatively low. In fact, the majority of known optimal difference systems of sets are for exceptionally noisy channels, requiring a substantial amount of bits for synchronization. To address this problem, we present constructions for difference systems of sets that allow for higher information rates while sacrificing optimality to only a small extent. Our constructions utilize optimal difference systems of sets as ingredients and, when applied carefully, generate asymptotically optimal ones with higher information rates. We also give direct constructions for optimal difference systems of sets with high information rates and error-tolerance that generate binary and ternary self-synchronizing codes.

Design of an Error-Tolerance Scheme for Discrete Wavelet Transform in JPEG 2000 Encoder

The JPEG 2000 image compression standard is designed for a broad range of data compression applications. The discrete wavelet transformation (DWT), central to the signal analysis and important in the JPEG 2000, is quite susceptible to computer-induced errors. The errors can be spread to many output transform coefficients if the DWT is implemented by using lifting scheme. This paper proposes an efficient error tolerance scheme (ETS) to detect errors occurring in DWT. A pipeline-based DWT structure is also developed in this paper to speed up the error detection process. The proposed ETS design uses weighting sums of the DWT coefficients at the output compared with an equivalent check value derived from the input-data. With the proposed ETS design, the errors introduced at DWT can be effectively detected. Additionally, the results of error detection can be further analyzed and evaluated to show the capability of error tolerance. Some standard images are used as test samples to verify the feasibility of the proposed ETS design. Experimental results and comparisons show that the proposed ETS has good performance in error detection time and error tolerance capability.

Fault Tolerance Design by Accurate SER Estimation Based on Ensemble Transform Matrix

With development of CMOS process, the minimum lithographic feature has now scaled down to regime of nano-scale. Integrated circuits (ICs) are becoming increasingly susceptible to uncertainty caused by soft errors, inherently probabilistic devices, and manufacturing variability. With all kinds of faults and errors, soft error is the most common and widespread. The different design methodology can reach different soft error tolerance ability, so we must find a way to estimate the soft error rate (SER) efficiently to make the design more fault tolerant. In this paper, we propose and investigate the ensemble transform matrix model. We show that the model can describe the actual nano-scale circuit performance. We also propose criteria to evaluate the circuits’ soft error tolerance capability. Simulation shows that the proposed ensemble transform matrix model is effective and suitable for CAD tools development in nano-scale circuit and system design.

Design of Asynchronous Circuits for High Soft Error Tolerance in Deep Submicrometer CMOS Circuits

As the devices are scaling down, the combinational logic will become susceptible to soft errors. The conventional soft error tolerant methods for soft errors on combinational logic do not provide enough high soft error tolerant capability with reasonably small performance penalty. This paper investigates the feasibility of designing quasi-delay insensitive (QDI) asynchronous circuits for high soft error tolerance. We analyze the behavior of null convention logic (NCL) circuits in the presence of particle strikes, and propose an asynchronous pipeline for soft-error correction and a novel technique to improve the robustness of threshold gates, which are basic components in NCL, against particle strikes by using Schmitt trigger circuit and resizing the feedback transistor. Experimental results show that the proposed threshold gates do not generate soft errors under the strike of a particle within a certain energy range if a proper transistor size is applied. The penalties, such as delay and power consumption, are also presented.

Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger

In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less.

Designing a Dependable and Fault-Tolerant Semiautonomous Distributed Control Data Collection Network With Opportunistic Hierarchy

This paper presents the satellite-linked data acquisition and photogrammetry (SLiDAP) network, designed to conduct shore-based, close-range 3-D imaging in remote areas. The lack of communications and power infrastructure and ability to service the system requires periodic, synchronous operations of multiple semiautonomous elements with a high degree of reliability. The SLiDAP system uses an opportunistic network architecture based on four distinct levels of control, to accommodate unpredictable operational constraints and failures. The synchronization of periodic tasks in a distributed control and remotely operable network are highlighted, and measures to increase the reliability of system operations are discussed, including hardware redundancy, intelligent watchdog timer, software error tolerance, self-repair, and remote update capability. The characteristics of the SLiDAP system within the concept of autonomic computing are discussed.