Error Floor Region Research Articles

A New Class of Braided Block Codes Constructed by Convolutional Interleavers

Parallel Concatenated Block (PCB) codes are conventionally represented as high-rate codes with low error correcting capability. To form a reliable and outstanding code, this paper presents a modification on the structure of PCB codes, which is accomplished by encoding some parity bits of one of their component codes. For the newly proposed code, named as the braided code, non-stuff bit-based convolutional interleavers are applied, aiming to minimize the design complexity while ensuring the proper permutations of the original message and selected parity bits. To precisely determine the error correcting capability, a tight bound for the minimum weight of braided code is presented. Additionally, further analyses are provided, which verify iterative decoding performance and the complexity of the constructed code. It is concluded that an outstanding braided code is formed by utilizing a reasonable number of iterations applied at its decoding processes, while maintaining its design complexity at a level similar to other well-known codes. The significant performance of short and long-length-based braided codes is evident in both waterfall and error floor regions.

Space–time labeling diversity for distributed Goppa-coded cooperative networks over Nakagami-[formula omitted] channels

This paper proposes the novel space–time labeling diversity for the distributed Goppa-coded cooperation (STLD-DGCC) scheme over the Nakagami-q fading channel to improve the performance of the short-to-medium information block transmission. Two different Goppa codes with the same information length are deployed in the source and the relay, respectively, with the Goppa code at the relay providing additional redundancy. Meanwhile, two distinct labeling mappers of M-ary quadrature amplitude modulation (M-QAM) are used in the novel space–time labeling diversity (STLD) to achieve the extra diversity gain and decrease the error floor (EF) region in the Goppa coding scheme. To lower the computational complexity of the maximum likelihood (ML) detection, a near-ML reduced-complexity (RC) detection approach that compromises the system performance and the computation complexity is proposed. In addition, two novel joint decoding algorithms based on the critical signal-to-noise ratio (SNR) threshold are presented at the destination, namely the parallel algorithm and serial algorithm, to enhance the overall performance of the proposed STLD-DGCC scheme. In the case of the Nakagami-q fading model, the analytical union bound of the average bit error probability is provided, which tightly matches the Monte Carlo simulated results at high SNR. The simulation results further indicate that the proposed STLD-DGCC scheme significantly outperforms both the corresponding non-cooperative Goppa coding scheme and the DGCC scheme without the STLD technique under identical conditions. Furthermore, the performance of the STLD-DGCC scheme surpasses that of the existing transmission scheme, offering a promising candidate for further small information block communications.

Block Markov superposition transmission of LDPC codes

In this paper, based on the block Markov superposition transmission (BMST) technique, we present a new class of coupled low-density parity-check (LDPC) codes for the transport block (TB)-based transmission to improve the error-correcting performance. For encoding, the previous LDPC codewords corresponding to a TB (at prior time slot) are interleaved and superimposed onto the current LDPC codewords, resulting in the transmitted codewords. For decoding, the sliding window decoding algorithm with sum-product or min-sum implementations can be employed, inheriting a relatively low-latency decoding. A distinguished advantage of the proposed coded transmission over spatially coupled LDPC (SC-LDPC) codes is that the encoder/decoder of the proposed codes can be designed by reusing the encoder/decoder architecture of component block LDPC codes. To analyze the waterfall performance of BMST-LDPC code ensembles, we present the protograph-based EXIT chart analysis, which can efficiently predict the error-correcting performance in waterfall region. To analyze the error-floor performance of BMST-LDPC codes, we employ the genie-aided (GA) lower bound, which can efficiently predict the error-correcting performance in error-floor region. For ease of implementation, the BMST-LDPC codes are constructed by taking the (2, 4)-raptor-like LDPC codes or the 5G LDPC codes as the basic components. The numerical results reveal that the proposed codes can have capacity-approaching performance, exhibiting a gap of 0.007 ​dB away from the corresponding Shannon limit. They also reveal that, by using the proposed BMST construction, the error-correcting performance of the original 5G block LDPC codes can be significantly improved, achieving coding gains up to one dB over the AWGN channels and two dB over the fast fading channels.

Adaptive Decoding Algorithm With Variable Sliding Window for Double SC-LDPC Coding System

In this letter, an adaptive decoding algorithm with a variable sliding window for joint source-channel coding (JSCC) scheme based on double spatially coupled low-density parity-check (DSC-LDPC) codes is investigated. For the traditional sliding window decoding (SWD) algorithm, one or more errors occurring in a decoding window may affect the decoding of the next window, which will trigger error propagation. To mitigate the effects, a window extension algorithm based on average log-likelihood ratios (LLRs) will be proposed, but the implement of extension implies higher decoding complexity. In order to trade-off the error rate performance and complexity, the source and channel threshold that determines the window extension are analyzed. In the simulation, the proposed SWD algorithm with acceptable complexity has better error rate performance in the water fall region and the error floor region.

A Semi Linear State Space Model for Error Floor Estimation of LDPC Codes Over the AWGN Channel

In this paper, we propose a novel state-space model to represent the behavior of sum-product algorithm (SPA) in the vicinity of a trapping set (TS) of a low-density parity-check (LDPC) code over the additive white Gaussian noise (AWGN) channel in the error floor region. The proposed model takes into account the non-linear behavior of SPA in the initial iterations using a quadratic approximation, and dynamically adjusts the operating point of the model in accordance to the statistical properties of TS messages. This is in contrast to the existing linear state-space models which linearly approximate the non-linear behavior of SPA at around the operating point of zero in all iterations. Simulation results are provided to demonstrate the higher accuracy of the proposed model in estimating the error floor of LDPC codes compared to the linear state-space model. We also make connections to the semi-analytical code-dependent technique proposed by Richardson for the error floor estimation of LDPC codes, and demonstrate that the proposed state-space model not only is a fully-analytical code-independent counterpart to that method, but also has less complexity and, in some cases, more accuracy.

Modified Convolutional Interleavers for Parallel Concatenated Block Codes

The letter presents a modification on the block-wise operation of convolutional interleavers for the Parallel Concatenated Block (PCB) codes. Interleaving is conducted so that every block of the interleaved data includes one bit of a message block. This leads to determining the minimum weight of PCB codes from messages with weight 1. Due to the insertion of some stuff bits in the permutation process, multiplicities of the minimum weight of the PCB’s constituent code is less than that obtained from the previously proposed interleavers. This improves the performance of code in its error floor region.

Performance analysis of LDPC coded GFDM systems

This paper analyzes the error probability performance of low-density parity-check (LDPC) coded generalized frequency division multiplexing (GFDM) systems over Rayleigh fading and additive white Gaussian noise (AWGN) channels. The initial log-likelihood ratio (LLR) expressions used in the sum-product algorithm (SPA) decoder are first derived for the system model presented in this paper. Based on the decoding threshold of the system, the frame error rate (FER) in the low E b / N 0 $E_b/N_0$ region is estimated by modeling the channel variations using the observed bit error rate (BER). Then, a lower bound based on the absorbing sets is proposed for FER when quantized SPA decoders are used. For AWGN channels, the lower bound can act as an estimate of the FER in the error-floor region if the absorbing set is dominant and its multiplicity is known. For Rayleigh channels, the lower bound can still be used to estimate the FER performance of selected codes. The estimation approach for the FER in the low E b / N 0 $E_b/N_0$ region and the lower bound on the FER in the high E b / N 0 $E_b/N_0$ region can be used as practical tools for evaluating different designs of GFDM-based systems in terms of the error probability performance. The quantization scheme has an important impact on the FER and BER performances. Randomly constructed and array-based LDPC codes are used to obtain numerical results that show the system performance and the accuracy of the proposed FER estimations.

Error Floor Analysis of LDPC Column Layered Decoders

In this letter, we analyze the error floor of column layered decoders, also known as shuffled decoders, for low-density parity-check (LDPC) codes under saturating sum-product algorithm (SPA). To estimate the error floor, we evaluate the failure rate of different trapping sets (TSs) that contribute to the frame error rate in the error floor region. For each such TS, we model the dynamics of SPA in the vicinity of the TS by a linear state-space model that incorporates the information of the layered message-passing schedule. Consequently, the model parameters and the failure rate of the TS change as a result of the change in the order by which the messages of different layers are updated. This, in turn, causes the error floor of the code to change as a function of scheduling. Based on the proposed analysis, we then devise an efficient search algorithm to find a schedule that minimizes the error floor. Simulation results are presented to verify the accuracy of the proposed error floor estimation technique.

Spatially coupled serially concatenated codes: Analysis and extension

Spatially coupled serially concatenated codes (SC-SCCs) perform well in the error floor region over additive white Gaussian noise (AWGN) channel. In this paper, firstly, we investigate the impact of the component codes on the performances of SC-SCCs. Simulation results show that, by properly selecting the component codes, we can trade off the performances of the SC-SCCs over the error floor region and the waterfall region. Secondly, we introduce a class of spatially coupled multiple-concatenated codes, the recursive-superposition-based SC-SCCs (RS-SC-SCCs). We derive the exact density evolution (DE) equations of the RS-SC-SCCs over the binary erasure channels (BECs). These equations can be used to guide the selection of the component codes and the coupling ratios. Simulation results over the AWGN channels show that the proposed RS-SC-SCCs perform better than the SC-SCC in both the waterfall region and the error floor region.

Improving bit error-rate based on adaptive Bose-Chaudhuri Hocquenghem concatenated with convolutional codes

Several algorithms have been proposed to avoid the error floor region, such as the concatenation codes that requires high computational demands in addition to high complexity. This paper proposes a technique based on using cascaded BCH and convolutional codes that leads to better error correction performance. Moreover, an adaptive method based on sensing the channel's noise to determine the number of the parity bits that will be added to the used BCH that reduces the consumed bandwidth and the transmitted parity bits is presented. A further enhancement is fulfilled by using parallel processing branches, resulting in reducing the consumed time and speed up the performance. The results show that the proposed code presents a better performance. A high reduction in the number of cycles that will be used in the encoding and decoding compared with the classical method and finally a flexible parity bits method based on the signal-to-noise ratio of the channel that reduced the parity bits which leads to reduce the consumed bandwidth. The MATLAB simulation and the field programmable gate array (FPGA) implementation will be provided in this paper to validate the proposed concept.

Experimental investigations on upstream transmission performances in future-proof THz-band indoor network based on photonics

The upstream transmission performance was experimentally investigated to consider the practical deployment of a photonics-based terahertz (THz)-band indoor network. An experimental setup was established using several off-the-shelf THz and optical components, to evaluate the technical feasibility of the uplink. Two commercialized THz mixers were used to build the THz wireless link, and a cost-effective 10 GHz-class directly modulated distributed feedback-laser diode (DFB-LD) was employed as an optical modulator to configure the optical link for a THz-band indoor network. The power penalty by the bandwidth-limited optical components was approximately 4 dB at 10−4 bit error rate (BER) when the data rate of the uplink was fixed at 30 Gb/s. It is worth noting that the interplay between the frequency chirp of the directly modulated DFB-LD and chromatic dispersion in the optical fiber significantly affects the BER. Owing to this interplay, the measured BER is seriously degraded at 30 Gb/s from 1.38 × 10−5 (without transmission) to 9.27 × 10−5 (10 km transmission), which is located in the error-floor region, however it still satisfies within 7% forward error correction (FEC) threshold (3.8 × 10−3). Subsequently, the BER curves over the wireless THz link were also measured. As a result, 30 Gb/s transmission over one m wireless and 10 km single-mode optical fiber distance was successfully demonstrated.

Systematic Convolutional Low Density Generator Matrix Code

In this paper, we propose a systematic low density generator matrix (LDGM) code ensemble, which is defined by the Bernoulli process. We prove that, under maximum likelihood (ML) decoding, the proposed ensemble can achieve the capacity of binary-input output symmetric (BIOS) memoryless channels in terms of bit error rate (BER). The proof technique reveals a new mechanism, different from lowering down frame error rate (FER), that the BER can be lowered down by assigning light codeword vectors to light information vectors. The finite length performance is analyzed by deriving an upper bound and a lower bound, both of which are shown to be tight in the high signal-to-noise ratio (SNR) region. To improve the waterfall performance, we construct the systematic convolutional LDGM (SysConv-LDGM) codes by a random splitting process. The SysConv-LDGM codes are easily configurable in the sense that any rational code rate can be realized without complex optimization. As a universal construction, the main advantage of the SysConv-LDGM codes is their near-capacity performance in the waterfall region and predictable performance in the error-floor region that can be lowered down to any target as required by increasing the density of the uncoupled LDGM codes. Numerical results are also provided to verify our analysis.

Errors and Erasures Decoding of Product Codes for Optical Transport Networks

A concatenated soft decision forward error correcting (FEC) coding scheme with an inner low density generator matrix (LDGM) code and an outer product code (PC) is considered for high-speed optical communications. We compare the performance of the concatenated coding scheme in which erasures are introduced at the output of the inner decoder to that of the scheme in which hard-decision is made at the input of inner decoder. An exact expression for the number of errors and erasures that are guaranteed to be decoded by the outer product code is derived. Then, an approach for deriving an approximation of the error probability for the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">erasure</i> + <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">error</i> decoder is proposed. Using this approach, optimal thresholds can be chosen for declaring erasures at the output of the inner decoder. It is shown that the codeword error rate for the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">error</i> + <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">erasure</i> iterative decoder is better than that of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">error only</i> iterative decoder in the error floor region.

Performance analysis of short length low density parity check codes

Outstanding bit error rate LDPC design in waterfall region and error floor region is one of the challenging tasks for the past decade. This chapter, focuses on the design of LDPC encoder with the low error floor and waterfall region of BER with minimum trapping set. Scheduled Progressive Edge-Growth (SPEG) LDPC encoder is used, and the simulation result of density evolution and exit chart are giving the better convergence of LDPC encoder. BER performance in error floor can controlled by minimum trapping set and waterfall region controlled by scheduled PEG LDPC encoder (1000, 500) with code length (n) is less than 600. The girth of the SPEG encoder is 8. SPEG with minimum trapping set will perform well for short length code also and it converges faster than the other PEG encoder.

ADMM Check Node Penalized Decoders for LDPC Codes

Alternating direction method of multipliers (ADMM) is an efficient implementation of linear programming (LP) decoding for low-density parity-check (LDPC) codes. By adding penalty terms to the objective function of the LP decoding model, ADMM variable node (VN) penalized decoding can suppress the non-integral solutions and improve the frame error rate (FER) performance in the low signal-to-noise ratio (SNR) region. In this paper, we propose a novel ADMM check node (CN) penalized decoding algorithm. Codeword solutions which satisfy all parity-check equations will have smaller penalty values than non-codeword solutions, including the non-integral solutions. We discuss the required properties of CN-penalty functions, propose a few functions that satisfy those properties, and study their performance/complexity trade-offs. We also investigate the convergence properties of the proposed algorithm and prove that its performance is independent of the transmitted codeword. Using Monte Carlo simulations and instanton analysis, we then demonstrate that the proposed CN-penalized decoder outperforms ADMM VN penalized decoders in both waterfall and error floor regions. This comes at the expense of some increase in the decoding complexity.

Spatially coupled serially concatenated codes via parity re‐encoding

The recently introduced spatially coupled turbo-like codes are attractive in trading-off performances between the error-floor region and the water-fall region. This letter is concerned with the construction of spatially coupled serially concatenated codes. Particularly, a new construction of spatially coupled serially concatenated codes is presented, in which a portion of the encoding output of the previous inner encoder is taken as the input of the current inner encoder. The authors show that by proper selection of the component codes and the re-encoding ratio, performance gain about 0.25 dB is obtained with the proposed construction.

Low Complexity Generalized-LDPC Decoder Based on Trellis Splicing

The high reliability short length low-density parity-check (LDPC) codes for Ultra Reliable Low Latency Communication (URLLC) are particularly important to future wireless communication systems. Even though the error floor region performance can be improved by using generalized-LDPC (G-LDPC) decoder, its penalty of increasing complexity can not be ignored. In this letter, we invoke the early stop criterion and the trellis splicing (TS) method to G-LDPC decoder. Hence, a G-LDPC-TS decoder is proposed. The proposed method can effectively reduce the number of variable nodes (VNs) involved in BCJR (Bahl-Cocke-Jelinek-Raviv) decoding of G-LDPC; thus, it yields a lower computational complexity. The results confirm that our G-LDPC-TS decoder can achieve a significant complexity reduction without sacrificing the performance.

A Channel-Aware Combinatorial Approach to Design High Performance Spatially-Coupled Codes

Because of their capacity-approaching performance and their complexity/latency advantages, spatially-coupled (SC) codes are among the most attractive error-correcting codes for use in modern dense data storage systems. SC codes are constructed by partitioning an underlying block code and coupling the partitioned components. Here, we focus on circulant-based SC codes. Recently, the optimal overlap (OO), circulant power optimizer (CPO) approach was introduced to construct high performance SC codes for additive white Gaussian noise (AWGN) and Flash channels. The OO stage operates on the protograph of the SC code to derive the optimal partitioning that minimizes the number of graphical objects that undermine the performance of SC codes under iterative decoding. Then, the CPO optimizes the circulant powers to further reduce this number. Since the nature of detrimental objects in the graph of a code critically depends on the characteristics of the channel of interest, extending the OO-CPO approach to construct SC codes for channels with intrinsic memory is not a straightforward task. In this paper, we tackle one relevant extension; we construct high performance SC codes for practical 1-D magnetic recording channels, i.e., partial-response (PR) channels. Via combinatorial techniques, we carefully build and solve the optimization problem of the OO partitioning, focusing on the objects of interest in the case of PR channels. Then, we customize the CPO to further reduce the number of these objects in the graph of the code. SC codes designed using the proposed OO-CPO approach for PR channels outperform prior state-of-the-art SC codes by up to around 3 orders of magnitude in frame error rate (FER) and 1.1 dB in signal-to-noise ratio (SNR). More intriguingly, our SC codes outperform structured block codes of the same length and rate by up to around 1.8 orders of magnitude in FER and 0.4 dB in SNR. The performance advantage of SC codes designed using the devised OO-CPO approach over block codes of the same parameters is not only pronounced in the error floor region, but also in the waterfall region.

1/n Turbo codes from linear system point of view

The performance of turbo codes at the error floor region is largely determined by the effective free distance, which corresponds to the minimum Hamming weight among all codeword sequences generated by input sequences of weight two. In this paper, we study turbo codes of dimension one obtained from the concatenation of two equal codes and present an upper bound on the effective free distance of a turbo code with these parameters defined over any finite field. We do that making use of the so-called (A, B, C, D) state-space representations of convolutional codes and restrict to the case where A is invertible. A particular construction, from a linear systems point of view, of a recursive systematic convolutional code of rate 1/n so that the effective free distance of the corresponding turbo code attains this upper bound is also presented.

QC-LDPC construction free of small size elementary trapping sets based on multiplicative subgroups of a finite field

Trapping sets significantly influence the performance of low-density parity-check codes. An $ (a, b) $ elementary trapping set (ETS) causes high decoding failure rate and exert a strong influence on the error floor of the code, where $ a $ and $ b $ denote the size and the number of unsatisfied check-nodes in the ETS, respectively. The smallest size of an ETS in $ (3, n) $-regular LDPC codes with girth 6 is 4. In this paper, we provide sufficient conditions to construct fully connected $ (3, n) $-regular algebraic-based QC-LDPC codes with girth 6 whose Tanner graphs are free of $ (a, b) $ ETSs with $ a\leq5 $ and $ b\leq2 $. We apply these sufficient conditions to the exponent matrix of a new algebraic-based QC-LDPC code with girth at least 6. As a result, we obtain the maximum size of a submatrix of the exponent matrix which satisfies the sufficient conditions and yields a Tanner graph free of those ETSs with small size. Some algebraic-based QC-LDPC code constructions with girth 6 in the literature are special cases of our construction. Our experimental results show that removing ETSs with small size contribute to have better performance curves in the error floor region.