Decoding Of Error-correcting Codes Research Articles

Optimized wireless communication for 6G signal processing using memory‐augmented deep unfolding network

SummaryIn this manuscript, optimized wireless communication for 6G signals processing using memory‐augmented deep unfolding network (WC‐6G‐SP‐MADUN) is proposed. The aim of this work is to give a memory‐augmented deep unfolding network approach with a focus on belief propagation decoding of error correction codes and multiple‐input multiple‐output (MIMO) wireless systems. In contrast, compares and tabulates the performance of memory‐augmented deep unfolding methodologies with classic principled procedures, which could potentially enable 6G. Here, the wireless communication for 6G signal processing methods was used for a variety of receiver functions, including self‐interference cancelation, signal estimation and detection using memory‐augmented deep unfolding Network (MADUN), and advanced error correction by clouded leopard optimization algorithm (CLOA). Furthermore, outline the general framework of memory‐augmented deep unfolding method for any kind of signal processing application and talk about cutting edge research paths that will make it possible to build communication networks in the future. The proposed approach is implemented in MATLAB; the performance is analyzed with performance metrics such as reliability, complexity, SNR gain, convergence rate, hardware efficiency, and quantization bit width. The proposed approach attains higher SNR gain 17.96%, 24.75%, and 30.09%; lower complexity 17.92%, 23.41%, and 30.13%; and higher convergence 18.01%, 25.41%, and 31.39% when analyzed with existing techniques such as redefined wireless communication for 6G: signal processing meets deep learning and deep unfolding (RWC‐6G‐SP‐DU), lower complication deep unfolded neural network receiver for MIMO under probability data association detector (LC‐DUNN‐MIMO‐PDAD), and deep learning in physical layer communications: evolution with prospects on 5G and 6G networks (DL‐PLC‐6G), respectively.

Lightweight Microcontroller with Parallelized ECC-Based Code Memory Protection Unit for Robust Instruction Execution in Smart Sensors.

Embedded systems typically operate in harsh environments, such as where there is external shock, insufficient power, or an obsolete sensor after the replacement cycle. Despite these harsh environments, embedded systems require data integrity for accurate operation. Unintended data changes can cause a serious error in reduced instruction set computer (RISC)-based small embedded systems. For instance, if communication is performed on an edge, where there is insufficient power supply, the peak threshold is not reached, resulting in data transmission failure or incorrect data transmission. To ensure data integrity, we use an error-correcting code (ECC), which can detect and correct errors. The ECC parity bit and data are stored together using additional ECC memory, and the original data are extracted through the ECC decoding process. The process of extracting the original data is executed in the instruction fetch stage, where a bottleneck appears in the RISC-based structure. When the ECC decoding process is executed in the bottleneck, the instruction fetch stage increases the instruction fetch time and significantly reduces the overall performance. In this study, we attempt to minimize the effect of ECC on the transmission speed by executing the ECC decoding process in parallel to improve speed by degrading the bottleneck. To evaluate the performance of a parallelized ECC decoding block, we applied the proposed method to the tiny processing unit (TPU) with a RISC-based von Neumann structure and compared memory usage, speed, and reliability according to different transmission success rates in each model. The experiment was conducted using a benchmark that repeatedly executed several 3*3 matrix calculations, and reliability improvement was compared by corrupting the stored random date to confirm the reliability of the transmission success rate. As a result, in the proposed model, using the additional parity bits for parallel processing, memory usage increased by 10 bits per instruction, reducing the data rate from 80 to 61%. However, it showed an improvement in overall reliability and a 7% increase in speed.

Perm2vec: Attentive Graph Permutation Selection for Decoding of Error Correction Codes

Error correction codes are an integral part of communication applications, boosting the reliability of transmission. The optimal decoding of transmitted codewords is the maximum likelihood rule, which is NP-hard due to the curse of dimensionality. For practical realizations, sub-optimal decoding algorithms are employed; yet limited theoretical insights prevent one from exploiting the full potential of these algorithms. One such insight is the choice of permutation in permutation decoding. We present a data-driven framework for permutation selection, combining domain knowledge with machine learning concepts such as node embedding and self-attention. Significant and consistent improvements in the bit error rate are introduced for all simulated codes, over the baseline decoders. To the best of the authors' knowledge, this work is the first to leverage the benefits of the neural Transformer networks in physical layer communication systems.

An Improved LDPC ECC based on System Level Reprogramming for MLC NAND Flash

With the ever-increasing requirement for higher performance of system and memory with a huge storage capacity, Multi-Level Cell (MLC) flash memory holds a dominant position in flash memory. However, more errors are observed in flash memory as the storage size increases. Thus, various error correction techniques (e.g., Hamming, BCH, LDPC) have been adopted to maintain the reliability of data stored in flash memory. Retention error, which occurs in data that is not accessed for a long period after stored, is the major contributor of flash memory error. The incidence of retention error is highly related to p-e (program-erase) cycle of flash memory. However, in system level, flash memory should be erased before modifying data even if ECC (Error correction code) decoding is completed. This erase operation increases the p-e cycle of flash memory, resulting in high incidence of retention error. This paper introduces a safe in-place reprogramming scheme at system level to optimally correct errors without erasing. Additionally, LDPC decoding scheme uses information about the uncorrected errors to improve the performance of the LDPC decoder. Through an experiment that simulates real NAND flash memory chips, safe reprogramming scheme at system level and proposed LDPC decoding method are explicitly demonstrated. As a result of proposed in-place reprogramming, reliable retention time of data is extended. Also, proposed LDPC decoding along with safe reprogramming scheme reduced the number of average iterations up to 33% while maintaining a robust correction ability.

Non-statistical Euclidean-distance SISO Decoding of Error-correcting Codes over Gaussian and Other Channels

Non-statistical Euclidean-distance SISO Decoding of Error-correcting Codes over Gaussian and Other Channels

Fast Decoding ECC for Future Memories

High-performance storage class memories could benefit from a fast decoding error correcting code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore, we propose an architecture for fast decoding of double and triple ECCs. In our architecture, any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular, the error locator polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here, we describe a gate-level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems

The efficiency and cost of silicon physically unclonable function (PUF)-based applications, and in particular key generators, are heavily impacted by the level of reproducibility of the bare PUF responses (PRs) under varying operational circumstances. Error-correcting codes (ECCs) can be used to achieve near-perfect reliability, but come at a high implementation cost especially when the underlying PUF is very noisy. When designing a PUF-based key generator, a more reliable PUF will result in a less complex ECC decoder and a smaller PUF footprint, and hence, an overall more efficient implementation. This paper proposes novel insight and resulting method for reducing noise on memory-based PRs, based on adapting supply voltage ramp-up time to ambient temperature. Circuit simulations on 45 nm low-power CMOS, as well as silicon measurements are presented to validate the proposed method. Our results demonstrate that choosing an appropriate voltage ramp-up for enrollment and adapting it according to the ambient temperature at key-reconstruction is a powerful method which makes memory-based PR noise up to 3× smaller. In addition, this paper investigates the competitiveness of integrating the proposed method in a commercial product; the investigation is done in two phases. First by determining the saved area, and second by implementing a circuit that maps the ambient temperature into an appropriate voltage ramp-up. The results show that the new system costs up to 82.1% less area while it delivers up to 3× higher reproducibility.

Overclocking NAND Flash Memory I/O Link in LDPC-Based SSDs

Due to the increasingly significant process variation and gradual Flash memory cell wear-out, the worst-case-oriented error correction code (ECC) in solid-state drives (SSDs) is mostly underutilized throughout the entire lifetime. Error-prone overclocking of Flash memory chip I/O links can trade such ECC underutilization for opportunistically improving SSD speed performance, and its effectiveness strongly depends on how well the ECC decoding can handle the overclocking-induced I/O link errors. As SSDs are quickly adopting low-density parity-check (LDPC) code, this brief concerns LPDC-based overclocked SSDs. Experiments with 20-nm NAND Flash memory chips reveal unique bit error characteristics of the overclocked I/O link, based upon which this brief develops solutions that can leverage the error characteristics to improve LDPC decoding performance. Results show that the developed techniques can reduce LDPC code decoding power consumption by 60% and reduce the decoding failure rate by over two orders of magnitude.

Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective

This paper advocates a time-aware design methodology for using multilevel per cell (MLC) phase-change memory (PCM) in data storage systems such as solid-state disk and disk cache. It is well known that phase-change material resistance drift gradually reduces memory device noise margin and degrades the raw storage reliability. Intuitively, due to the time-dependent nature of resistance drift, if we can dynamically adjust storage system operations adaptive to the time and, hence, memory cell resistance drift, we may improve various PCM-based data storage system performance metrics. Under such an intuitive time-aware system design concept, we propose three specific design techniques, including time-aware variable-strength error correction code (ECC) decoding, time-aware partial rewrite, and time-aware read-&-refresh. Since PCM-based data storage systems have to use powerful ECC whose decoding can be energy-hungry, the first technique aims to minimize the ECC decoding energy consumption. The second technique improves the data retention limit when using partial rewrite in MLC PCM, and the third technique can further improve the efficiency of time-aware variable-strength ECC decoding. Using hypothetical 2-bit/cell PCM with device parameters from recent device research as a test vehicle, we carry out mathematical analysis and trace-based simulations, which show that these techniques can improve the data retention limit by few orders of magnitude, and enable up to 97 and 79 percent energy savings for PCM-based solid-state disk and PCM-based disk cache.

Memory Reliability Improvement Based on Maximized Error-Correcting Codes

Error-correcting codes (ECC) offer an efficient way to improve the reliability and yield of memory subsystems. ECC-based protection is usually provided on a memory word basis such that the number of data-bits in a codeword corresponds to the amount of information that can be transferred during a single memory access operation. Consequently, the codeword length is not the maximum allowed by a certain check-bit number since the number of data-bits is constrained by the width of the memory data interface. This work investigates the additional error correction opportunities offered by the absence of a perfect match between the numbers of data-bits and check-bits in some widespread ECCs. A method is proposed for the selection of multi-bit errors that can be additionally corrected with a minimal impact on ECC decoder latency. These methods were applied to single-bit error correction (SEC) codes and double-bit error correction (DEC) codes. Reliability improvements are evaluated for memories in which all errors affecting the same number of bits in a codeword are independent and identically distributed. It is shown that the application of the proposed methods to conventional DEC codes can improve the mean-time-to-failure (MTTF) of memories with up to 30 %. Maximized versions of the DEC codes are also proposed in which all adjacent triple-bit errors become correctable without affecting the maximum number of triple-bit errors that can be made correctable.

Sparse Solution of Underdetermined Systems of Linear Equations by Stagewise Orthogonal Matching Pursuit

Finding the sparsest solution to underdetermined systems of linear equations y = Φx is NP-hard in general. We show here that for systems with “typical”/“random” Φ, a good approximation to the sparsest solution is obtained by applying a fixed number of standard operations from linear algebra. Our proposal, Stagewise Orthogonal Matching Pursuit (StOMP), successively transforms the signal into a negligible residual. Starting with initial residual r0 = y, at the s -th stage it forms the “matched filter” ΦTrs-1, identifies all coordinates with amplitudes exceeding a specially chosen threshold, solves a least-squares problem using the selected coordinates, and subtracts the least-squares fit, producing a new residual. After a fixed number of stages (e.g., 10), it stops. In contrast to Orthogonal Matching Pursuit (OMP), many coefficients can enter the model at each stage in StOMP while only one enters per stage in OMP; and StOMP takes a fixed number of stages (e.g., 10), while OMP can take many (e.g., n). We give both theoretical and empirical support for the large-system effectiveness of StOMP. We give numerical examples showing that StOMP rapidly and reliably finds sparse solutions in compressed sensing, decoding of error-correcting codes, and overcomplete representation.

A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift

Because of its promising scalability potential and support of multilevel per cell storage, phase-change memory has become a topic of great current interest. However, recent studies show that structural relaxation effect makes the resistance of phase-change material drift over the time, which can severely degrade multilevel per cell phase-change memory storage reliability. This makes powerful memory fault tolerance solutions indispensable, where error correction code (ECC) will play an essential role. This work aims to develop fault tolerance solutions that can effectively compensate memory cell resistance drift. First, based upon information-theoretical study, we show that conventional use of ECC, which is unaware of memory content lifetime, can only achieve the performance with a big gap from the information-theoretical bounds. This motivates us to study the potential of time-aware memory fault tolerance, where the basic idea is to keep track the memory content lifetime and use this lifetime information to accordingly adjust how memory cell resistance is quantized and interpreted for ECC decoding. Under this time-aware fault tolerance framework, we study the use of two types of ECCs, including classical codes such as BCH that only demand hard-decision input and advanced codes such as low-density parity-check (LDPC) codes that demand soft-decision probability input. Using hypothetical four-level per cell and eight-level per cell phase-change memory with BCH and LDPC codes as test vehicles, we carry out extensive analysis and simulations, which demonstrate very significant performance advantages of such time-aware memory fault tolerance strategy in the presence of significant memory cell resistance drift.

Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache

It is almost evident that SRAM-based cache memories will be subject to a significant degree of parametric random defects if one wants to leverage the technology scaling to its full extent. Although strong multibit error-correcting codes (ECC) appear to be a natural choice to handle a large number of random defects, investigation of their applications in cache remains largely missing arguably because it is commonly believed that multibit ECC may incur prohibitive performance degradation and silicon/energy cost. By developing a cost-effective L2 cache architecture using multibit ECC, this paper attempts to show that, with appropriate cache architecture design, this common belief may not necessarily hold true for L2 cache. The basic idea is to supplement a conventional L2 cache core with several special-purpose small caches/buffers, which can greatly reduce the silicon cost and minimize the probability of explicitly executing multibit ECC decoding on the cache read critical path, and meanwhile, maintain soft error tolerance. Experiments show that, at the random defect density of 0.5 percent, this design approach can maintain almost the same instruction per cycle (IPC) performance over a wide spectrum of benchmarks compared with ideal defect-free L2 cache, while only incurring less than 3 percent of silicon area overhead and 36 percent power consumption overhead.

Tradeoff functions for constrained systems with unconstrained positions

We introduce a new method for analyzing and constructing combined modulation and error-correcting codes (ECCs), in particular codes that utilize some form of reverse concatenation and whose ECC decoding scheme requires easy access to soft information. We expand the work of Immink and Wijngaarden and also of Campello, Marcus, New, and Wilson, in which certain bit positions in the modulation code are deliberately left unconstrained for the ECC parity bits, in the sense that such positions can take on either bit value without violating the constraint. Our method of analysis involves creating a single graph that incorporates information on these unconstrained positions directly into the constraint graph without any assumptions of periodicity or sets of unconstrained positions, and is thus completely general. We establish several properties of the tradeoff function that relates the density of unconstrained positions to the maximum code rate. In particular, the tradeoff function is shown to be concave and continuous. Algorithms for computing lower and upper bounds for this function are presented. We also show how to compute the maximum possible density of unconstrained positions and give explicit values for the runlength-limited (RLL(d,k)) and maximum-transition-run (MTR(j,k)) constraints.

Belief networks, hidden Markov models, and Markov random fields: A unifying view

The use of graphs to represent independence structure in multivariate probability models has been pursued in a relatively independent fashion across a wide variety of research disciplines since the beginning of this century. This paper provides a brief overview of the current status of such research with particular attention to recent developments which have served to unify such seemingly disparate topics as probabilistic expert systems, statistical physics, image analysis, genetics, decoding of error-correcting codes, Kalman filters, and speech recognition with Markov models.