Error Control Capability Research Articles

Application of Fuzzy Reasoning with Fusion Rules in Intelligent Information Processing

The core of artificial intelligence (AI) research is intelligent information processing, and fuzzy reasoning and fuzzy neural networks are significant research areas in models of intelligent information processing. The study examines the robustness of fuzzy reasoning by using the property characteristics of triangular modal operators and implication operators, which are used to analyse the Lipschitz property of fuzzy operators and its corresponding property characteristics of triangular modal operators and implication operators. Inference operators are used to investigate the robustness and error-control capabilities of fuzzy operators for fuzzy reasoning. The results showed that the robustness of quasi-copula fuzzy reasoning with fusion rules is better, and the corresponding maximum output perturbation is lowest at 0.36 when the fuzzy operator is T[Formula: see text]&R[Formula: see text] and the corresponding maximum output error is lowest at 0.41 when the fuzzy operators are T[Formula: see text]&R[Formula: see text] and T[Formula: see text]&R[Formula: see text]. This shows the optimal performance of the fuzzy associative memory model with fuzzy rule for quasi-copula fuzzy operators and can improve the theoretical technology. The best-performance fuzzy copula operator of the fuzzy associative memory model can enhance the theoretical foundation and technical support for the processing of intelligent information.

IRS-aided NOMA-based communication architecture for 6G wireless networks: An enhanced error-control and reliable data transmission

Intelligent reflecting surface (IRS) is a key technology for sixth-generation (6G) wireless communication to obtain high energy and spectral efficiency with a minimum cost. On the other hand, non orthogonal multiple access (NOMA) enhances the spectrum efficiency of the network. The combining schemes are implemented to obtain error-free data at the receiver. This paper proposes an IRS-aided NOMA-based packet combining (PC) and aggressive packet combining (APC) schemes-assisted communication architecture to enhance service quality and achieve sustainable and resilient connectivity among users for 6G wireless networks. In this paper, the mathematical model has been derived for the instantaneous achievable data rate, bit error rate, outage probability, and packet correction capability. The derived analytical expressions are validated through detailed Monte Carlo simulations. The obtained results show that the proposed schemes outperform the conventional NOMA with PC and NOMA with APC schemes and facilitate enhanced error control and reliable data transmission capabilities. Moreover, the proposed schemes have been compared with the IRS-aided orthogonal multiple access (OMA) schemes, where IRS-aided OMA schemes are considered benchmarks of the proposed schemes. It is presented that the proposed schemes are superior to the conventional OMA with PC and APC schemes and IRS-aided OMA with PC and APC schemes.

Software-Defined GPU-CPU Empowered Efficient Wireless Federated Learning With Embedding Communication Coding for Beyond 5G

Currently, with the widespread of the intelligent internet of things (IoT) in beyond 5G, wireless federated learning (WFL) has attracted a lot of attention to enable knowledge construction and sharing among a huge amount of distributed edge devices. However, under unstable wireless channel conditions, existing WFL schemes exist the following challenges: First, learning model parameters will be disturbed by bit errors because of interference and noise during wireless transmission, which will affect the training accuracy and the loss of the learning model. Second, traditional edge devices with CPU acceleration are inefficient due to the low throughout computation, especially in accelerating the encoding and decoding process during wireless transmission. Third, current hardware-level GPU acceleration methods cannot optimize complex operations, for instance, complex wireless coding in the WFL environment. To address the above challenges, we propose a software-defined GPU-CPU empowered efficient WFL architecture with embedding LDPC communication coding. Specifically, we embed wireless channel coding into the server weight aggregation and the client local training process respectively to resist interruptions in the learning process and design a GPU-CPU acceleration scheme for this architecture. The experimental results show its anti-interference ability and GPU-CPU acceleration ability during wireless transmission, which is 10 times the error control capability and 100 times faster than existing WFL schemes.

Inertial Motion Capture Accuracy Improvement by Kalman Smoothing and Dynamic Networks

Localization-capable inertial motion capture algorithms rely on zero-velocity updates (ZUPT), usually as measurements in a Kalman filtering scheme, for position and attitude error control. As ZUPTs are only applicable during the static phases a link goes through, estimation errors grow during dynamic ones. This error growth may somewhat be mitigated by imposing biomechanical constraints in multi-sensor systems. Error reduction is also possible by optimization-based methods that incorporate the dynamic and static constraints governing the system behavior over a period of time (e.g. the dynamic network algorithm); when this period includes multiple static phases for a link, its estimation accuracy is greatly improved. The current study enhances the error control capabilities of an existing inertial motion capture algorithm by multi-stage smoothing. The base algorithm benefits from imposing biomechanical constraints and is self-calibrating with respect to body geometry and some sensor parameters. The smoothing process, conducted over the stepping periods of each foot, comprises two stages; Kalman smoothing followed by error minimization by dynamic networks. The performance of the algorithm, deployed using both extended and square-root unscented Kalman filtering schemes (EKF and SRUKF, respectively), is experimentally evaluated during a fast-paced walking test using a custom-made inertial motion capture system. A comparison with an optical motion capture system showed that the proposed method decreased pelvis position and attitude estimation errors by 19% and 29%, respectively. Furthermore, compared to the EKF-based smoothing algorithm, the SRUKF-based method proved to be more successful in error reduction and parameter estimation.

Reduced-Order Computational-Fluid-Dynamics-Based Analysis of Aviation Heat Exchangers

The goal envisioned for the Reduced-Order Computational Fluid Dynamics and Heat Transfer (ROM-CFDHT) procedure is obtaining fast turnaround in simulation time so that computational fluid dynamics can form a component of a system-level design tool. To accomplish this, a set of finite-element schemes is proposed, including the choice of the quadratic interpolation functions, the penalty approach, an intelligent error-control capability, a continuation method, a restart procedure that restores the integrity of the error-control scheme when the procedure encounters difficulties, and the consistent flux method. It is shown that for a natural convection problem simulation using fewer than 20 elements produces Nusselt number results that agree with models using thousands of elements, with simulation time in seconds rather than hours. Forced convection over an asymmetrically laidout bank of tubes is simulated as another test of the proposed procedure. Three values of the Reynolds number, , 100, 1000 are investigated using two grids with significantly different levels of resolution and quality. The local distributions of show some differences between the grids, but the mean results are comparable. The coarse grid could not calculate the case due to poor resolution and grid quality. A combination of grid resolution and choice of schemes enables successful simulation.

Mitigation of Inter-Cell Interference in Flash Memory With Capacity-Approaching Variable-Length Constrained Sequence Codes

We propose using variable-length constrained sequence codes to mitigate inter-cell interference (ICI) in all-bit-line flash memory with multi-page programming for single-level cell, multi-level cell, and triple-level cell flash memory structures. We outline constraints that mitigate ICI in these systems based on an observation of the Gray mapping of data symbols, and we derive the capacity of each constraint. Based on a finite state machine representation of each constraint, we construct variable-length constrained sequence codes with code rates very close to capacity to mitigate ICI in these flash memories. We then exploit the inherent error control capability of the proposed constrained sequence codes to alleviate error propagation. Finally, we integrate these codes with error control codes and present simulation results that demonstrate the enhanced bit error rate performance that can be achieved.

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead.

An Efficient Overlapped LDPC Decoder with a Upper Dual-diagonal Structure

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual- diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non- overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

Performance analysis of stack decoding on block coded modulation schemes using tree diagram

The channel encoder adds redundancy in a structured way to provide error control capability. Modulator converts the symbol sequences from the channel encoder into waveforms which are then transmitted over the channel. Usually channel coder and modulator are implemented independently one after the other. But in a band limited channel better coding gains without sacrificing signal power are achieved when coding is combined with modulation. Block Coded Modulation (BCM) is such a scheme that results from the combination of linear block codes and modulation. In this paper we are proposing a stack decoding of rate 2/3 and rate 1/2 BCM schemes using tree structure and performance is compared with the Viterbi decoding that uses trellis representation. Simulation result shows that at reasonable bit error rate stack decoder performance is just 0.2 to 0.5 dB inferior to that of Viterbi decoding. Since stack decoding is a near optimum decoding scheme and whose decoding procedure is adaptable to noise level, we can consider this method in place of Viterbi decoding which is optimum and its decoding complexity grows exponentially with large code lengths.

A Flexible Parallel Simulator for Networks-on-Chip With Error Control

This paper presents a flexible parallel simulator to evaluate the impact of different error control methods on the performance and energy consumption of networks-on-chip (NoCs). Various error control schemes can be inserted into the simulator in a plug-and-play manner for evaluation. Moreover, a highly tunable fault injection feature is developed for modeling various fault injection scenarios, including different fault injection rates, fault types, fault injection locations, and faulty flit types. Case studies performed in the proposed flexible simulation environment are presented to demonstrate the impact of a set of error control schemes on NoC performance and energy in different noise scenarios. This paper also uses the simulator to provide design guidelines for NoCs with error control capabilities.

DC-Free Error-Control Block Codes

DC-free codes and error-control (EC) codes are widely used in digital transmission and storage systems. To improve system performance in terms of code rate, bit-error rate (BER), and low-frequency suppression, and to provide a flexible tradeoff between these parameters, this paper introduces a new class of codes with both dc-control and EC capability. The new codes integrate dc-free encoding and EC encoding, and are decoded by first applying standard EC decoding techniques prior to dc-free decoding, thereby avoiding the drawbacks that arise when dc-free decoding precedes EC decoding. The dc-free code property is introduced into standard EC codes through multimode coding techniques, at the cost of minor loss in BER performance on the additive white Gaussian noise channel, and some increase in implementation complexity, particularly at the encoder. This paper demonstrates that a wide variety of EC block codes can be integrated into this dc-free coding structure, including binary cyclic codes, binary primitive BCH codes, Reed-Solomon codes, Reed-Muller codes, and some capacity-approaching EC block codes, such as low-density parity-check codes and product codes with iterative decoding. Performance of the new dc-free EC block codes is presented.

동기 능력을 보유한 변형된 BCH 부호

본 논문에서는 통신 시스템에서 발생하는 에러를 정정 및 검출하기 위한 새로운 부호와 그 복호 방식을 제안하였다. 데이터 0의 런 길이를 제한하고 데이터 1의 최소 밀도를 증가시키기 위하여 (15, 7) BCH 부호를 변형하였으며 전체 패리티 비트를 추가하였다. 제안된 부호는 (16, 7) 블록 부호이며 비트 클럭 신호의 재생 능력과 높은 에러 제어 능력을 가지고 있다. 제안된 부호에서 데이터 0의 런 길이는 7 이하이고, 데이터 1의 밀도는 1/8 이상이며 최소 해밍 거리가 6임을 입증하였다. 제안된 부호를 사용하였을 때의 복호 에러 확률, 에러 검출 확률, 바른 복호 확률을 제시하였다. 기존의 다른 방식들에 비하여 오류 제어 능력이 우수함을 확인할 수 있었다. A new code and its decoding scheme are proposed. With this code, we can correct and detect the errors in communication systems. To limit the runlength of data 0 and augment the minimum density of data 1, a (15, 7) BCH code is modified and an overall parity bit is added. The proposed code is a (16, 7) block code which has the bit clock signal regeneration capability and high error control capability. It is proved that the runlength of data 0 is less than or equal to 7, the density of data 1 is greater than or equal to 1/8, and the minimum Hamming distance is 6. The decoding error probability, the error detection probability and the correct decoding probability are presented for the proposed code. It is shown that the proposed code has better error control capability than the conventional schemes.

Shape nature of error-control codes

In this paper we demonstrate that the perception of a shape property within error-control codes provides an alternative insight to their error-control capability. This insight may lead to the development of a new class of error-control codes based on shapes. To demonstrate the concept of shape, we illustrate the shape nature of convolutional codes within the Viterbi, maximum a posteriori, and Turbo decoding algorithms. We also introduce the concept of shape codes, in which binary information digits are mapped onto predefined imaginary shapes within a given signal constellation, and make use of these predefined shapes to provide a coding gain at very low signal-to-noise ratios, with a penalty of a reduction in the information throughput.

Partial-prefix synchronizable codes

A new class of codes for frame synchronization is proposed. Commonly, the beginning of every fixed or variable-length frame is identified by a given contiguous sequence called a prefix. To avoid the occurrence of the prefix elsewhere in the frame, a prefix synchronizable code (PS-code) is used. PS-codes have the property that the prefix does not occur in any codeword or in any concatenation of codewords in any position other than the first position. The new codes, termed partial-prefix synchronizable codes (PPS-codes), use a fixed sequence of symbols that is interspersed with symbols that carry information. The contiguous sequence from the first fixed symbol to the last fixed symbol is called a partial-prefix. Consequently, not one but a set of possible prefixes is used, and none of these prefixes is allowed to occur at any other than the first position of a codeword. The cardinality of PPS-codes is determined, and coding algorithms are proposed which have a computational complexity proportional to the length of the codewords. It is demonstrated that in comparison with PS-codes, PPS-codes have similar coding and prefix detection complexity, but they have a larger code size and have better error control capabilities.

Maximum runlength-limited codes with error control capabilities

New methods are presented to protect maximum runlength-limited sequences against random and burst errors and to avoid error propagation. The methods employ parallel conversion techniques and enumerative coding algorithms that transform binary user information into constrained codewords. The new schemes have a low complexity and are very efficient. The approach can be used for modulation coding in recording systems and for synchronization and line coding in communication systems. The schemes enable the usage of high-rate constrained codes, as error control can be provided with similar capabilities as for unconstrained sequences.

Single-track circuit codes

Single-track circuit codes (STTCs) are circuit codes with codewords of length n such that all the n tracks which correspond to the n distinct coordinates of the codewords are cyclic shifts of the first track. These codes simultaneously generalize single-track Gray codes and ordinary circuit codes. They are useful in angular quantization applications in which error detecting and/or correcting capabilities are needed. A parameter k, called the spread of the code, measures the strength of this error control capability. We consider the existence of STCCs for small lengths n/spl les/17 and spreads k/spl les/6, constructing some optimal and many good examples. We then give a general construction method for STCCs which makes use of ordinary circuit codes. We use this construction to construct examples of codes with 360 and 1000 codewords which are of practical importance. We also use the construction to prove a general result on the existence of STCCs for general spreads.

General and self-consistent method for the calibration of polarization modulators, polarimeters, and Mueller-matrix ellipsometers

Calibration of polarization-state generators (PSG's), polarimeters, and Mueller-matrix ellipsometers (MME's) is an important factor in the practical use of these instruments. A new general procedure, the eigenvalue calibration method (ECM), is presented. It can calibrate any complete MME consisting of a PSG and a polarimeter that generate and measure, respectively, all the states of polarization of light. In the ECM, the PSG and the polarimeter are described by two 4 x 4 matrices W and A, and their 32 coefficients are determined from three or four measurements performed on reference samples. Those references are smooth isotropic samples and perfect linear polarizers. Their optical characteristics are unambiguously determined during the calibration from the eigenvalues of the measured matrices. The ECM does not require accurate alignment of the various optical elements and does not involve any first-order approximation. The ECM also displays an efficient error control capability that can be used to improve the MME behavior. The ECM is illustrated by an experimental calibration, at two wavelengths (458 and 633 nm), of a MME consisting of a coupled phase modulator associated with a prism division-of-amplitude polarimeter.

A Navigation System for Mobile Service Robots

The determination of the momentary absolute position provides the basis for any path planning and navigation purposes of mobile service robots. Here, a navigation system is proposed which uses floor tiles that contain random patterns for the determination of the robot's absolute position. These random patterns offer powerful error control capabilities and allow a robust navigation in an everyday environment. Therefore, the proposed localization system is especially suited for service robots. Both the design of the decoding processes as well as the architecture of the localization system are considered. The paper closes with the discussion of the experiments which demonstrate the performance of the system, and with a set of conclusions we drew from this work.

A class of error control codes for byte organized memory systems-SbEC-(Sb+S)ED codes

A new class of error control codes, single byte error correcting and single byte plus single bit error detecting codes, are presented. The codes are suitable for semiconductor memory systems organized in a b-bit-per-chip manner, b/spl ges/2, and more efficient than previously known codes with as strong error control capabilities.

Construction of systematic codes for unidirectional error control

Construction methods for systematic t-UEC d-UED codes are proposed. These are codes that are able to simultaneously correct up to t unidirectional errors and detect from t+1 up to d unidirectional errors. Both encoding and decoding procedures are provided. The efficiency of the codes is discussed and compared to the efficiencies of known corresponding codes with slightly stronger or weaker error control capabilities.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>