Equivalent Throughput Research Articles

Distributed Caching in Converged Networks: A Deep Reinforcement Learning Approach

Content caching is an effective technique to alleviate the burden on backhaul links and reduce the traffic in cellular networks. In converged networks, broadcasting networks can push non-real-time popular services to different types of terminals during off-peak hours, while cellular networks are deployed to meet personalized needs. However, the storage capacity of terminals are usually limited. In this context, we study on the converged networks to push and cache the popular services in the router nodes close to the terminators. In this scheme, the most popular services are transmitted by the broadcasting base station and cached in the router nodes in a distributed cache network. Then, users can access the cached services in a more energy efficient manner. Due to the limited storage capacity of the router node, we assume that the user can access the cached services within two hops. Then, we formulate the service scheduling problem as a Markov Decision Process, aiming to maximize equivalent throughput (ET). Due to the large state space involved in the distributed cache network, it is quite challenging to obtain a tractable solution by the classical optimization algorithms. To handle this problem, a deep reinforcement learning based framework is proposed to tackle this problem. The simulation results show that the proposed algorithms are very effective; and they outperform the conventional one in term of the ET, especially when the users in the network subject to Poisson point process distribution.

In-Memory PageRank Accelerator With a Cross-Point Array of Resistive Memories

In-memory computing with cross-point arrays of resistive memory is a promising technique for typical tasks, such as the training and inference of deep learning. Recently, it has been shown that a cross-point array of resistive switching memory (RRAM) with a feedback configuration can be used to solve linear systems, compute eigenvectors, and rank webpages in just one step. Here, we demonstrate the PageRank with a real data set (the Harvard500) and an eight-level RRAM model, describing the conductance update, the standard deviation of each level, and the conductance ratio. By carefully placing each memory conductance value via a program-verify technique, we show that an accuracy of 95% can be achieved for the ranking result. The equivalent throughput of the eigenvector circuit for PageRank is estimated to be 0.183 tera-operations per second (TOPS), while the energy efficiency is 362 TOPS/W. This article supports the feasibility of in-memory PageRank with significant improvements in speed and energy efficiency for practical big-data tasks.

Distributed Caching Mechanism for Popular Services Distribution in Converged Overlay Networks

With the proliferation of portable devices, the exponential growth of the global mobile traffic brings great challenges to the traditional communication networks and the traditional wireless communication technologies. In this context, converged networks and cache-based data offloading have drawn more and more attention based on the strong correlation of services. This paper proposes a novel popular services pushing and caching scheme by using converged overlay networks. The most popular services are pushed by terrestrial broadcasting networks. And they are cached in ${n}$ router-nodes with limited cache sizes. Each router-node only interconnects with its neighbor nodes. Users are served through the router’s WiFi link. If the services requested are cached in the routers, the user can be immediately responded; otherwise, the requests can be responded through the link from cellular stations to the router. In the proposed scheme, the cache size of the router, the maximum number of requests each router can serve, and the whole-time delay are limited. Three node-selecting and dynamic programming algorithms are adopted to maximize the equivalent throughput. Analytical and numerical results demonstrate that the proposed scheme is very effective.

A resource scheduling scheme for spectrum aggregation in cognitive radio based heterogeneous networks

In spectrum aggregation (SA), two or more component carriers (CCs) of different bandwidths in different bands can be aggregated to support wider transmission bandwidth. The current resource scheduling schemes for spectrum aggregation are not optimal or suitable for CR based heterogeneous networks (HetNets). Consequently, the authors propose a novel resource scheduling scheme for spectrum aggregation in CR based HetNets, termed as cognitive radio based resource scheduling (CR-RS) scheme. CR-RS has a three-level structure. Under a dynamic traffic model, an equivalent throughput of the CCs based on the knowledge of primary users (PUs) is given. On this basis, the CR users data transmission time of each CC is equal in CR-RS. The simulation results show that CR-RS has the better performance than the current resource scheduling schemes in the CR based HetNets. Meanwhile, CR-RS is also effective in other spectrum aggregation systems which are not CR based HetNets.

A comparative study between spiral-filter press and belt press implemented in a cloudy apple juice production process

In this study, advantages and disadvantages of the innovative, low-oxygen spiral-filter press system were studied in comparison with the belt press, commonly applied in small and medium size enterprises for the production of cloudy apple juice. On the basis of equivalent throughput, a higher juice yield could be achieved with spiral-filter press. Also a more turbid juice with a higher content of suspended solids could be produced. The avoidance of enzymatic browning during juice extraction led to an attractive yellowish juice with an elevated phenolic content. Moreover, it was found that juice produced with spiral-filter press demonstrates a higher retention of phenolic compounds during the downstream processing steps and storage. The results demonstrates the advantage of the use of a spiral-filter press in comparison with belt press in the production of a high quality cloudy apple juice rich in phenolic compounds, without the use of oxidation inhibiting additives.

The Portable Chemical Sterilizer (PCS), D-FENS, and D-FEND ALL: novel chlorine dioxide decontamination technologies for the military.

There is a stated Army need for a field-portable, non-steam sterilizer technology that can be used by Forward Surgical Teams, Dental Companies, Veterinary Service Support Detachments, Combat Support Hospitals, and Area Medical Laboratories to sterilize surgical instruments and to sterilize pathological specimens prior to disposal in operating rooms, emergency treatment areas, and intensive care units. The following ensemble of novel, 'clean and green' chlorine dioxide technologies are versatile and flexible to adapt to meet a number of critical military needs for decontamination(6,15). Specifically, the Portable Chemical Sterilizer (PCS) was invented to meet urgent battlefield needs and close critical capability gaps for energy-independence, lightweight portability, rapid mobility, and rugged durability in high intensity forward deployments(3). As a revolutionary technological breakthrough in surgical sterilization technology, the PCS is a Modern Field Autoclave that relies on on-site, point-of-use, at-will generation of chlorine dioxide instead of steam. Two (2) PCS units sterilize 4 surgical trays in 1 hr, which is the equivalent throughput of one large steam autoclave (nicknamed "Bertha" in deployments because of its cumbersome size, bulky dimensions, and weight). However, the PCS operates using 100% less electricity (0 vs. 9 kW) and 98% less water (10 vs. 640 oz.), significantly reduces weight by 95% (20 vs. 450 lbs, a 4-man lift) and cube by 96% (2.1 vs. 60.2 ft(3)), and virtually eliminates the difficult challenges in forward deployments of repairs and maintaining reliable operation, lifting and transporting, and electrical power required for steam autoclaves.

A reconfigurable fabric for accelerating large-scale datacenter services

Datacenter workloads demand high computational capabilities, flexibility, power efficiency, and low cost. It is challenging to improve all of these factors simultaneously. To advance datacenter capabilities beyond what commodity server designs can provide, we have designed and built a composable, reconfigurablefabric to accelerate portions of large-scale software services. Each instantiation of the fabric consists of a 6x8 2-D torus of high-end Stratix V FPGAs embedded into a half-rack of 48 machines. One FPGA is placed into each server, accessible through PCIe, and wired directly to other FPGAs with pairs of 10 Gb SAS cables In this paper, we describe a medium-scale deployment of this fabric on a bed of 1,632 servers, and measure its efficacy in accelerating the Bing web search engine. We describe the requirements and architecture of the system, detail the critical engineering challenges and solutions needed to make the system robust in the presence of failures, and measure the performance, power, and resilience of the system when ranking candidate documents. Under high load, the largescale reconfigurable fabric improves the ranking throughput of each server by a factor of 95% for a fixed latency distribution--- or, while maintaining equivalent throughput, reduces the tail latency by 29%

New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Distributed arithmetic (DA)-based computation is popular for its potential for efficient memory-based implementation of finite impulse response (FIR) filter where the filter outputs are computed as inner-product of input-sample vectors and filter-coefficient vector. In this paper, however, we show that the look-up-table (LUT)-multiplier-based approach, where the memory elements store all the possible values of products of the filter coefficients could be an area-efficient alternative to DA-based design of FIR filter with the same throughput of implementation. By operand and inner-product decompositions, respectively, we have designed the conventional LUT-multiplier-based and DA-based structures for FIR filter of equivalent throughput, where the LUT-multiplier-based design involves nearly the same memory and the same number of adders, and less number of input register at the cost of slightly higher adder-widths than the other. Moreover, we present two new approaches to LUT-based multiplication, which could be used to reduce the memory size to half of the conventional LUT-based multiplication. Besides, we present a modified transposed form FIR filter, where a single segmented memory-core with only one pair of decoders are used to minimize the combinational area. The proposed LUT-based FIR filter is found to involve nearly half the memory-space and <formula formulatype="inline"> <tex Notation="TeX">$(1/N)$</tex></formula> times the complexity of decoders and input-registers, at the cost of marginal increase in the width of the adders, and additional <formula formulatype="inline"><tex Notation="TeX">$\sim(4N\times W)$</tex></formula> AND-OR-INVERT gates and <formula formulatype="inline"> <tex Notation="TeX">$\sim(2N\times W)$</tex></formula> NOR gates. We have synthesized the DA-based design and LUT-multiplier based design of 16-tap FIR filters by Synopsys Design Compiler using TSMC 90 nm library, and find that the proposed LUT-multiplier-based design involves nearly 15% less area than the DA-based design for the same throughput and lower latency of implementation. </para>

High Rate CPFSK Space-Time Trellis Codes

Space-time trellis coding is an established diversity technique that reduces the effects of multipath fading over wireless communication channels. Here, we consider high rate space-time trellis codes (STTC) with continuous phase frequency shift keying (CPFSK). We present optimized rate-2/3 STTC implemented with 3 transmit antennas. These codes provide system throughputs of 4 and 6 bits per channel use with 4-ary and 8-ary CPFSK respectively. Simulated error rate performance of the optimized codes with receive diversity is presented. We show that although the schemes do not achieve full transmit diversity, they provide excellent coding gains compared to full rank schemes that have equivalent throughput, but higher order modulations and greater complexity.

Evaluation of Variable Maximum Green Time to Improve Rural Traffic Signal Operations

Rural agencies frequently struggle to provide reasonable traffic signal operations because they lack the financial resources and traffic expertise common to larger cities. More advanced traffic signal controllers have many features that might help. One such feature is variable maximum green time (VMGT), also called the dynamic maximum, which allows the controller to continually adjust the maximum green in response to changes in traffic demand. Rural traffic signal operations are compared, given optimized timing with rural traffic signal control operations using a generic set of VMGT parameters. The research method included the use of software-in-the-loop simulation with VISSIM as the traffic simulation model and Econolite ASC/3 traffic controller software. Results from one high-volume and one low-volume site indicate that compared with optimized timings, a generic set of VMGT parameters can provide equivalent throughput, nearly equivalent average intersection delays, reasonable cycle lengths, and a more equal distribution of delay among approaches and movements.

Scaling of Spatial Reuse and Saturation Throughput in a Class of MAC Protocols

In this paper, we investigate the spatial reuse and saturation throughput of static ad-hoc networks with unbiased medium access control (MAC) protocols. Under the stochastic assumptions of our model, we obtain the upper bound on the equivalent saturation throughput of such MAC protocols as a function of node density. We also obtain the scaling properties of the spatial reuse and saturation throughput.

WLAN security processor

A novel wireless local area network (WLAN) security processor is described in this paper. It is designed to offload security encapsulation processing from the host microprocessor in an IEEE 802.11i compliant medium access control layer to a programmable hardware accelerator. The unique design, which comprises dedicated cryptographic instructions and hardware coprocessors, is capable of performing wired equivalent privacy, temporal key integrity protocol, counter mode with cipher block chaining message authentication code protocol, and wireless robust authentication protocol. Existing solutions to wireless security have been implemented on hardware devices and target specific WLAN protocols whereas the programmable security processor proposed in this paper provides support for all WLAN protocols and thus, can offer backwards compatibility as well as future upgrade ability as standards evolve. It provides this additional functionality while still achieving equivalent throughput rates to existing architectures.

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators

The PICO-NPA system automatically synthesizes nonprogrammable accelerators (NPAs) to be used as co-processors for functions expressed as loop nests in C. The NPAs it generates consist of a synchronous array of one or more customized processor datapaths, their controller, local memory, and interfaces. The user, or a design space exploration tool that is a part of the full PICO system, identifies within the application a loop nest to be implemented as an NPA, and indicates the performance required of the NPA by specifying the number of processors and the number of machine cycles that each processor uses per iteration of the inner loop. PICO-NPA emits synthesizable HDL that defines the accelerator at the register transfer level (RTL). The system also modifies the user's application software to make use of the generated accelerator. The main objective of PICO-NPA is to reduce design cost and time, without significantly reducing design quality. Design of an NPA and its support software typically requires one or two weeks using PICO-NPA, which is a many-fold improvement over the industry norm. In addition, PICO-NPA can readily generate a wide-range of implementations with scalable performance from a single specification. In experimental comparison of NPAs of equivalent throughput, PICO-NPA designs are slightly more costly than hand-designed accelerators. Logic synthesis and place-and-route have been performed successfully on PICO-NPA designs, which have achieved high clock rates.

Reduction and Approximation of Stochastic Petri Nets with Multiple-Input Multiple-Output Modules

Motivated by the success of reduction methods for analysis of ordinary Petri nets, researchers have produced significant results for reduction of generalized stochastic Petri nets (GSPN). Based on single-input single-output modular reduction, they, however, are not applicable to highly interacting discrete event systems. This paper presents a more generalized method based on the multiple-input multiple-output (MIMO) modules. It formulates concepts of MIMO modules, associated nets, and equivalent throughput nets and then presents rules and procedure for approximation of GSPN. The method is illustrated through a flexible manufacturing system.

Matrix–vector multiplication using digital partitioning for more accurate optical computing

Digital partitioning offers a flexible means of increasing the accuracy of an optical matrix-vector processor. This algorithm can be implemented with the same architecture required for a purely analog processor, which gives optical matrix-vector processors the ability to perform high-accuracy calculations at speeds comparable with or greater than electronic computers as well as the ability to perform analog operations at a much greater speed. Digital partitioning is compared with digital multiplication by analog convolution, residue number systems, and redundant number representation in terms of the size and the speed required for an equivalent throughput as well as in terms of the hardware requirements. Digital partitioning and digital multiplication by analog convolution are found to be the most efficient algorithms if coding time and hardware are considered, and the architecture for digital partitioning permits the use of analog computations to provide the greatest throughput for a single processor. To our knowledge this is the first study to propose the use of digital partitioning for optical matrix processing.

Trellis coding of quadrature frequency/phase modulated signals

The authors explore the trellis coding of continuous-phase quadrature frequency/phase modulated (CPQFPM) signal sets and continuous-phase FPM (CPFPM) signal sets, which are embodiments of the quadrature biorthogonal modulation (QBOM) technique. Conventional TCM and multiple TCM schemes with these modulation formats are examined using both the AWGN channel and the Rician fading channel design. Asymptotic coding gains in d/sup 2/(free) are tabulated for trellis-coded rate 3/4, 5/6, and 6/7 QFPM schemes, in comparison with uncoded modulations (8AMPM, 32AMPM) and other trellis-coded modulations (TCM (2FSK/4PSK 16QAM, 64QAM), MTCM (2FSK/8PSK)) of equivalent throughput rate. Performance gains on the Rician fading channel are demonstrated by increased values of the design parameters for this channel, namely symbol diversity L/sub min/ and branch distance product P. >

The Influence of Fast Infrared Firing on Thick Film Materials

Because of increasing concern with rising energy and equipment costs, greater emphasis is being placed on identifying units and processes with improved throughput and/or operating cost reductions. Recent utilization of the near infrared firing process, which was developed for metallizing solar cells with thick film materials [1] has resulted in its consideration by the hybrid circuit industry [2]. The differences in heat transfer between wire-wound conventional and near infrared furnaces are discussed. Test procedures and results are then described for Heraeus-Cermalloy resistor and conductor materials. The analytical and performance tests show equivalent or improved performance with near infrared (IR) firing. Finally an operating cost comparison of conventional wire-wound and IR furnaces with equivalent throughput shows that substantial savings result from using IR firing.

Merged Arithmetic

The concept of merged arithmetic is introduced and demonstrated in the context of multiterm multiplication/addition. The merged approach involves synthesizing a composite arithmetic function (such as an inner product) directly instead of decomposing the function into discrete multiplication and addition operations. This approach provides equivalent arithmetic throughput with lower implementation complexity than conventional fast multipliers and carry look-ahead adder trees.