Equivalent Parasitic Capacitance Research Articles

A 7.6-ns Delay Subthreshold Level-Shifter Leveraging a Composite Transistor and a Voltage-Controlled Current Source

A novel level shifter (LS) circuit that uses a new low-power approach based on a parasitic capacitance voltage controlled current source is presented to minimize the propagation delay (PD) and maximize the voltage conversion range. This new scheme uses a simplified circuit including a dependent current source, a composite transistor made of three interconnected n-channel MOSFETs (TnM), one CMOS input inverter, and one CMOS output buffer to provide a fast response time. The circuit utilizes the combined action of the equivalent parasitic capacitance of the TnM, the value of which changes dynamically according to the transient value of the input voltage, and the dependent current source to shift the input signal level up from subthreshold voltage levels to +3.0 V, with minimal delay and power consumption. The LS circuit fabricated in 0.35 μm CMOS technology occupies a silicon area of only 25 μm×25 μm. The LS shows measured rising and falling PDs of, respectively, 4 and 11.2 ns. The measured results show that the presented circuit outperforms other solutions over a wide frequency range of 1 to 130 MHz. The fabricated circuit consumes a static power 31.5 pW and a dynamic power of 3.4 pJ per transition at 1 kHz, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDL</sub> =0.8 V, and a capacitive load of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</sub> =0.1 pF.

A design technology of a wideband mm-wave injection-locked frequency divider

A design technology of the wideband mm-wave injection-locked frequency divider (ILFD) is proposed and based on the 40-nm CMOS technology, a relating chip is designed for verification. In order to solve the problem of the narrow locking range (LR) in conventional mm-wave ILFDs, the transformer-based high-order resonator is utilized to generate the rippled phase response, enlarging the LR efficiently; Additionally, for the propose of reducing the equivalent parasitic capacitance from the gate of differential pairs in mm-wave band, an inductive divider feedback technology is proposed, realizing the boost of oscillation frequency. Besides, the injection-locked conditions of phase and gain for a modified model are theoretically deduced and the enhancement of oscillation frequency is analyzed and verified by simulations. The layout is drawn and the parasitic parameters are extracted to acquire the post-simulation results which suggest a LR of 36.9% from 52.6~76.4 GHz under 0.8 V power supply while a LR of 45.1% from 50~79.1 GHz, consuming 2.9 mW achieving an FoM of 10.0 GHz/mW under 0.62 V supply voltage.

A Cascaded Gate Driver Architecture to Increase the Switching Speed of Power Devices in Series Connection

This article presents a cascaded gate driver (CGDA) architecture to improve the switching speed of series-connected power devices. The main idea is to propose a new technique to increase dV/dt of the devices when their voltages are already balanced. In complex power converters such as multicell and multilevel topologies, and series-connected power devices, many driver circuits are required and implemented. In such converters, there are several dV/dt sources generated at different floating points associated with the parasitic capacitances of the isolated barriers of the gate drivers (supplies and control signal isolation units), which can amplify the conducted electromagnetic interference (EMI) perturbations, and therefore, the switching speed of the power devices can be affected. This article is focused on the analysis of a new cascaded configuration of gate drivers to increase the switching speed and, consequently, reducing the switching losses of the series-connected transistor topologies. This improvement is achieved by reducing the equivalent parasitic capacitance of the gate driver circuitry considering the gate driver architectures: a new concept of cascaded gate driver is presented. Theoretical and experimental measurements are used to support the cascade gate driver architecture proposed in this article.

Analytical estimation of parasitic capacitances in high‐voltage switching transformers

Parasitic capacitances in transformers consist of three main groups: winding-to-winding, layer-to-layer, and stray capacitances. Stray capacitance is also made of turn-to-turn and turn-to-core capacitances. This study presents a novel analytical method for calculating the values of turn-to-turn, turn-to-core, and stray capacitances in each winding, and employs the results to calculate the equivalent parasitic capacitance especially for high-voltage switching transformers. The proposed analytical method introduces an explicit formula in terms of the winding and core dimensions. This formula can be applied in performance analysis and design optimisation methods. By utilising the proposed formula, calculation of the equivalent parasitic capacitance neither takes a great deal of time nor requires a particular computer system. The analytical results are verified by simulation results using the finite-element method and experimental results achieved by a practical prototype of a high-voltage switching transformer employed in a 390 W, 15 kV inductor–capacitor–inductor–capacitor resonant converter.

Frequency control of self‐sustained push‐pull resonant converter using effective parasitic capacitances

A method to control the frequency of a self-sustained push-pull converter at megahertz (MHz) level is proposed by utilising the parasitic capacitances of the circuit. As the equivalent parasitic capacitance and the frequency of the converter can be controlled by a DC voltage, the converter works as a voltage-controlled oscillator and a phase locked loop (PLL) controller is developed to lock in the zero-voltage switching frequency under circuit parameter variations such as the load, the coupling coefficient etc. The effect of the parasitic capacitances on the operating frequency and why the DC voltage can control it are analysed in details with equivalent circuit analysis and simulation study. Practical experiments demonstrate that the PLL controller can lock the operating frequency within 20–30 MHz with relatively good waveforms.

A Dual-Wideband CMOS LNA Using Gain–Bandwidth Product Optimization Technique

This paper presents a dual-wideband, common-gate, cascode low-noise amplifier (LNA) using gain---bandwidth product optimization technique. This approach shrinks the aspect ratio of the cascode MOS device, thereby reducing the equivalent parasitic capacitance of the resonator load to optimize the gain---bandwidth product of the LNA. The input impedance of the proposed LNA is analyzed, and the noise factor is well predicted through analytical equations. Measurement results that show well agreement with post-simulation results demonstrate the feasibility of this technique. In low-band mode, experimental results presented a maximum $$\left| S_{21} \right| $$S21 of 13.4 dB over a $$-$$-3-dB bandwidth of 3.1---4.8 GHz with a minimum noise figure of 4.5 dB. In high-band mode, the proposed LNA achieved a maximum $$\left| S_{21} \right| $$S21 of 13.6 dB with a minimum noise figure of 6.2 dB over a $$-$$-3-dB bandwidth of 7.3---9.4 GHz. A test chip with a die area of 0.83 mm$$^{2}$$2 was fabricated using a 0.18 $$\upmu $$μm CMOS process. The proposed dual-wideband LNA consumes 9.1 mW, excluding the buffer, from a supply voltage of 1.8 V.

A Generalized Common-Mode Current Cancelation Approach for Power Converters

The interwinding parasitic capacitance of transformers and the parasitic capacitance between semiconductor switches and the ground are two major contributors to the common-mode (CM) noise currents in switched mode power converters. In this paper, a generalized CM current cancelation approach is proposed for the reduction of CM noise in isolated power converters. The approach is demonstrated in a forward converter. In this approach, the total effect of the two parasitic capacitances on CM noise is represented with an equivalent parasitic capacitance (EPC) at low frequencies. With this EPC, different CM current cancelation techniques can be efficiently organized to simultaneously cancel the low-frequency CM noise caused by these two parasitic capacitances. Furthermore, the EPC can be used to evaluate and quantify the performance of CM noise reduction techniques. Both theoretical analysis and experimental results show that the proposed approach is easy to implement and can significantly attenuate low frequency CM noise and therefore greatly reduce CM filter size and cost.

Detailed Derivation and Minimization of the Equivalent Parasitic Capacitances of a High-Voltage Multiplier Based on the Complete Model

The authors' previous paper presents the complete model of parasitic capacitances in a high-voltage (HV) multiplier in the HV generator in a medical X-ray machine. The equivalent parasitic capacitance of the multiplier C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> based on the model is exhibited to interpret the role of the parasitic capacitances in circuit operation of the generator. Without derivation of the analytical expression of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> , its dependence on the component parameters is directly shown, which leads to guidelines for minimization of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> . However, the complete capacitance model has a complicated structure and contains voltage-dependent capacitances and voltage sources, which gives complexity to derivation of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> as well as difficulties to clear understanding of the voltage dependence of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> . Thus, this paper presents the detailed derivation and analytical expression of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> . Exactly speaking, the key part of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> , namely, the total chain capacitance C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dcht</sub> that determines the voltage dependence of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> , is conducted. A simple way is presented for the derivation of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dcht</sub> . The derivation enables a clear understanding of the voltage dependence of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dcht</sub> . Moreover, a design procedure for minimization of C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> is created, accompanied by a case study. It gives designers step-by-step rules to make an optimal HV multiplier with a minimum C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">em</sub> .

Modelling of maximum power efficiency of charge pump circuits

The loss estimation in a switched-capacitor DC–DC converter has caused much controversy because of the uncertainty of the contribution of device parasitics to the power efficiency of a converter. Beginning from a simple equivalent circuit model, a closed-form solution to the maximum achievable power efficiency of a converter in which both the effects of parasitic resistance and capacitance are taken into account is presented. It has been observed that the peak power efficiency of a Dickson charge pump depends mainly on the equivalent parasitic capacitance of a given technology and its operation mode, which is governed by the choices of the coupling capacitance, on-resistance of the switch, as well as the operation frequency of the circuit.

A 6-$\mu$W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology

An output-capacitorless low-dropout regulator (LDO) compensated by a single Miller capacitor is implemented in a commercial 90-nm CMOS technology. The proposed LDO makes use of the small transistors realized in nano-scale technology to achieve high stability, fast transient performance and small voltage spikes under rapid load-current changes without the need of an off-chip capacitor connected at the LDO output. Experimental result verifies that the proposed LDO is stable for a capacitive load from 0 to 50 pF (estimated equivalent parasitic capacitance from load circuits) and with load capability of 100 mA. Moreover, the gain-enhanced structure provides sufficient loop gain to improve line regulation to 3.78 mV/V and load regulation to 0.1 mV/mA, respectively. The embedded voltage-spike detection circuit enables pseudo Class-AB operation to drive the embedded power transistor promptly. The measured power consumption is only 6 μW under a 0.75-V supply. The maximum overshoot and undershoot under a 1.2-V supply are less than 66 mV for full load current changes within 100-ns edge time, and the recovery time is less than 5 μs.