Equivalent Finite State Machine Research Articles

Generating test sequences from a set of MSCs

We propose an approach to generate test cases from a set of Message Sequence Charts (MSCs) by constructing a semantically equivalent finite state machine for testing reactive and embedded software. Test cases are expressed as a sequence of messages to be exchanged among various system entities. We use scenario activation conditions and state assignments to generate only the feasible states and transitions. This paper uses complex digital TV software to illustrate how test cases are automatically generated.

Heterogeneous Petri net methodology for the design of complex controllers

A controller design methodology based on Petri nets is developed. The semantics of the method, and the algorithm for the construction of an equivalent finite state machine make use of both synchronous and asynchronous marking graphs giving rise to the name 'heterogeneous Petri nets'. The method allows the designer of a controller greater freedom in the use of well structured graphics specifying the controller while the supporting CAD tool ensures an efficient (in the sense of clock-cycle usage) derivation of an equivalent finite state machine.

A New Approach to Hierarchical and Statistical Timing Simulations

This paper describes a new approach for timing analysis in general and, more specifically, for statistical timing analysis. A methodology based upon the utilization of the design hierarchy for circuit partitioning and building of the simulation hierarchy was developed. The logic and timing behaviors of the blocks resulting from the partitioning are dissociated and modeled separately. The logic model is represented by an equivalent finite state machine while an automated characterization process extracts the timing data from multiple circuit simulations in order to build a parametric timing model. These models provide the basis of an event-driven hierarchical timing simulator which can be used as a stand-alone tool but also as a front end for statistical timing analyses. Both the nominal and the statistical simulators have been implemented within STAT! (Statistical Timing Analysis Tool), and the results obtained for a few test cases are presented here.