Entropy Decoding Research Articles

Implementation of JPEG XS entropy encoding and decoding on FPGA

AbstractJPEG XS is the latest international standard for shallow compression fields launched by the International Organization for Standardization (ISO). The coding standard was officially released in 2019. The JPEG XS standard can be encoded and decoded on different devices, but there is no research on the implementation of JPEG XS entropy codec on FPGAs. This paper briefly introduces JPEG XS encoding, proposes a modular design scheme of encoder and decoder on FPGA for the entropy encoding and decoding part, and parallelizes the algorithm in JPEG XS coding standard according to the characteristics of FPGA parallelization processing, mainly including low-latency optimization design, storage space optimization design. The optimized scheme in this paper scheme enables encoding speeds of up to 4 coefficients/clock and decoding speeds of up to 2 coefficients/clock, with a 75% reduction in encoding and decoding time. The maximum clock frequency of the entropy encoder is about 222.6 MHz, and the maximum clock frequency of the entropy decoder is about 127 MHz. The design and implementation of the FPGA-based JPEG XS entropy encoding and decoding algorithm is of great significance and provides ideas for the subsequent implementation and optimization of the entire JPEG XS standard on FPGAs. This work is the first in the world to propose the design and implementation of an algorithm that can implement the JPEG XS entropy encoding and decoding process on FPGA. It creates the possibility for the effective application of JPEG XS standard in more media.

Digital Image Decoder for Efficient Hardware Implementation

Increasing the resolution of digital images and the frame rate of video sequences leads to an increase in the amount of required logical and memory resources necessary for digital image and video decompression. Therefore, the development of new hardware architectures for digital image decoder with a reduced amount of utilized logical and memory resources become a necessity. In this paper, a digital image decoder for efficient hardware implementation, has been presented. Each block of the proposed digital image decoder has been described. Entropy decoder, decoding probability estimator, dequantizer and inverse subband transformer (parts of the digital image decoder) have been developed in such way which allows efficient hardware implementation with reduced amount of utilized logic and memory resources. It has been shown that proposed hardware realization of inverse subband transformer requires 20% lower memory capacity and uses less logic resources compared with the best state-of-the-art realizations. The proposed digital image decoder has been implemented in a low-cost FPGA device and it has been shown that it requires at least 32% less memory resources in comparison to the other state-of-the-art decoders which can process high-definition frame size. The proposed solution also requires effectively lower memory size than state-of-the-art architectures which process frame size or tile size smaller than high-definition size. The presented digital image decoder has maximum operating frequency comparable with the highest maximum operating frequencies among the state-of-the-art solutions.

A Real-Time Ultra-High Definition Video Decoder of AVS3 on Heterogeneous Systems

Recent years have witnessed the exponential increase in the demand for ultra high definition (UHD) video compression. The third generation of Audio Video Coding Standard (AVS3), which is also known as IEEE Standard 1857.10, is the latest audio and video coding standard developed by the China AVS working group. In AVS3, targeting for UHD videos, a series of efficient coding tools have been introduced, leading to the dramatical increase of computational burden. In this scenario, real-time decoding of UHD videos becomes extremely challenging. This paper presents an improved hybrid CPU + GPU accelerated framework for AVS3 decoding. In particular, the motion vector (MV) derivation process is extracted from entropy decoding threads on the CPU. Therefore, the dependency between threads is removed and the entropy decoding can be performed by multiple threads efficiently. Regarding the GPU, we design compact data structures for transform, prediction, and in-loop filtering to reduce the burden of data transmission. A flexible information buffer supporting multi-thread random writing is further created to coordinate the computation between CPU and GPU. Through asynchronous operations on the buffer, the computation of different computing units and the data transmission between them could be performed in parallel. With NVIDIA GeForce RTX 2080Ti GPU and Intel Core i7 8700K CPU, the proposed decoder achieves 151 frames per second (fps) for 4K videos and 55 fps for 8K videos in all intra configuration. In random access configuration, 218 fps and 74 fps are obtained for 4K and 8K videos, respectively.

Error Exponents for Asynchronous Multiple Access Channels, Controlled Asynchronism May Outperform Synchronism

Exponential error bounds achievable by universal coding and decoding are derived for frame-asynchronous discrete memoryless multiple access channels with two senders, via the method of subtypes, a refinement of the method of types. An empirical entropy decoder is employed. A key tool is an improved packing lemma, that overcomes the technical difficulty caused by codeword repetitions via an induction based new argument. The asymptotic form of the bounds admits numerical evaluation. This demonstrates that error exponents achievable by synchronous transmission can be superseded via controlled asynchronism, i.e. a deliberate shift of the codewords.

Design and ARM-Based Implementation of Bitstream-Oriented Chaotic Encryption Scheme for H.264/AVC Video.

In actual application scenarios of the real-time video confidential communication, encrypted videos must meet three performance indicators: security, real-time, and format compatibility. To satisfy these requirements, an improved bitstream-oriented encryption (BOE) method based chaotic encryption for H.264/AVC video is proposed. Meanwhile, an ARM-embedded remote real-time video confidential communication system is built for experimental verification in this paper. Firstly, a 4-D self-synchronous chaotic stream cipher algorithm with cosine anti-controllers (4-D SCSCA-CAC) is designed to enhance the security. The algorithm solves the security loopholes of existing self-synchronous chaotic stream cipher algorithms applied to the actual video confidential communication, which can effectively resist the combinational effect of the chosen-ciphertext attack and the divide-and-conquer attack. Secondly, syntax elements of the H.264 bitstream are analyzed in real-time. Motion vector difference (MVD) coefficients and direct-current (DC) components in Residual syntax element are extracted through the Exponential-Golomb decoding operation and entropy decoding operation based on the context-based adaptive variable length coding (CAVLC) mode, respectively. Thirdly, the DC components and MVD coefficients are encrypted by the 4-D SCSCA-CAC, and the encrypted syntax elements are re-encoded to replace the syntax elements of the original H.264 bitstream, keeping the format compatibility. Besides, hardware codecs and multi-core multi-threading technology are employed to improve the real-time performance of the hardware system. Finally, experimental results show that the proposed scheme, with the advantage of high efficiency and flexibility, can fulfill the requirement of security, real-time, and format compatibility simultaneously.

Medical image encryption and compression by adaptive sigma filterized synorr certificateless signcryptive Levenshtein entropy-coding-based deep neural learning

Pre-processing of medical images plays a vibrant part in the field of medicine to detect patient’s disease at an earlier stage. Hospitals and medical centers generate an enormous volume of digital medical images day by day, which is used for several purposes of diagnostic procedures. Because of many images,for secured transmission, image compression is required to reduce the redundancies in the image and to accomplish the proficient image communication. To reduce the redundancies in the image and to accomplish the proficient communication of images. A competent Adaptive sigma filterized synorr certificateless signcryptive Levenshtein entropy coding-based deep neural learning (ASFSCSLEC-DNL) technique is presented to develop the image encryption and compression. The main goal of the ASFSCSLEC-DNL technique was to improve the security level of medical image transmission. The deep feed-forward artificial neural network was applied in the ASFSCSLEC-DNL technique for medical image pre-processing, encryption, and compression with multiple layers. The adaptive sigma filter was employed to denoise the medical image. The medical image encryption and signature generation were done with synorr certificateless signcryption. Finally, Levenshtein entropy encoding was applied to compress images. Then the compressed image was sent to the receiver where the decompression and decryption are implemented using Levenshtein entropy decoding and synorr certificateless decryption. Investigational estimation was carried out in chest X-ray medical images and the results of ASFSCSLEC-DNL technique proved more capable in terms of higher peak signal to noise ratio and compression ratio with lesser encryption time compared to the existing state-of-the-art methods.

A residual network framework based on weighted feature channels for multispectral image compression

Deep learning has achieved great success in many computer vision tasks, such as recognition, image enhancement and image compression. However, it is difficult to use a residual network that can efficiently consider the characteristics of multispectral images for multispectral image compression. In this paper, a novel end-to-end multispectral image compression framework based on a weighted feature channel residual network is proposed to efficiently remove the spatial and spectral redundancy of multispectral images by extracting the importance of each channel. The multispectral image compression framework includes a forward coding network, a rate-distortion optimizer, a quantizer/inverse quantizer, an entropy encoder/decoder and an inverse decoding network. In the encoder, multispectral images are directly fed into the forward coding network, and the main spectral and spatial features of the multispectral images are extracted by the residual block. Additionally, the weighted feature channel module can explicitly model the relationship between feature channels when extracting features from multispectral images and adaptively allocate different weights for each feature channel through training. The rate-distortion optimizer is added to make the main features compact. Then, the intermediate feature data are quantized and encoded by lossless entropy coding to obtain a code stream. In the decoder, the code stream is approximately restored to the intermediate features through the entropy decoder and the inverse quantizer. Then, the intermediate features are reconstructed to the multispectral images by the inverse decoding network. Experimental results on 7-band multispectral images of the Landsat 8 satellite and 8-band multispectral images of WorldView-3 satellite demonstrate that the proposed algorithm can achieve a better PSNR than conventional 2D schemes (which are JPEG2000 and JPEG in this paper) and 3D scheme (which is 3D-SPIHT in this paper) and can effectively preserve more spectral information of multispectral images.

Efficient and Effective Context-Based Convolutional Entropy Modeling for Image Compression.

Precise estimation of the probabilistic structure of natural images plays an essential role in image compression. Despite the recent remarkable success of end-to-end optimized image compression, the latent codes are usually assumed to be fully statistically factorized in order to simplify entropy modeling. However, this assumption generally does not hold true and may hinder compression performance. Here we present contextbased convolutional networks (CCNs) for efficient and effective entropy modeling. In particular, a 3D zigzag scanning order and a 3D code dividing technique are introduced to define proper coding contexts for parallel entropy decoding, both of which boil down to place translation-invariant binary masks on convolution filters of CCNs. We demonstrate the promise of CCNs for entropy modeling in both lossless and lossy image compression. For the former, we directly apply a CCN to the binarized representation of an image to compute the Bernoulli distribution of each code for entropy estimation. For the latter, the categorical distribution of each code is represented by a discretized mixture of Gaussian distributions, whose parameters are estimated by three CCNs. We then jointly optimize the CCNbased entropy model along with analysis and synthesis transforms for rate-distortion performance. Experiments on the Kodak and Tecnick datasets show that our methods powered by the proposed CCNs generally achieve comparable compression performance to the state-of-the-art while being much faster.

Design of CABAC Entropy Decoding, Inverse Quantization, Inverse Transform Blocks of H.264 Decoder using Verilog HDL

Video compression/decompression is a term used to define a method for compressing or decompressing digital video. There are different video compression /decompression standards. H.264 which is also known as Advanced Video Coding is a paradigm, most commonly used these days. The objective of developing H.264 is to devise a standard which can impart good quality of video at a nether bit rates as compared to previous standards. To improve compression efficiency, H.264 encoders/decoders uses complex algorithms and modes which require more power. From studies we know that software-based implementations of these encoders/decoders on DSPs and CPUs suffer by few real time limitations. Hence hardware implementation of video encoders and decoders are necessary. Here in this paper Entropy decoding, Inverse Transform and Inverse Quantization blocks of H.264 Video decoder are designed using Verilog and simulated by Xilinx ISE Simulator

An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder

This paper proposes two decoder hardware architectures for the tabled asymmetric numeral systems (tANS) compression algorithm, a software implementation of which is used by Apple and Facebook due to its efficiency. To the best of our knowledge, hardware architectures for the highly efficient tANs algorithm are investigated by the authors so far uniquely. The tANS decoder hardware architectures have been compared to a novel Huffman decoder hardware architecture because the Huffman coding is known as one of the fastest coding techniques in hardware and software. For the proposed architectures, the decoding throughput is highly dependent on the compression ratio of data. Experimental results show that the proposed tANS architecture outperforms the tANS software decoder and can achieve the throughput up to 200MB/s using current FPGA technology. Compared to canonical Huffman decoder the proposed hardware architecture provides up to four times higher decoding throughput.

A High Throughput JPEG2000 Entropy Decoding Unit Architecture

This paper is dedicated to a hardware architecture development for JPEG2000 entropy decoding unit (EDU) which consist of two parts: context modeling unit (CMU) and arithmetic decoding unit (ADU). To achieve a high throughput we propose an efficient pixel skipping scheme to save clock cycles for non-context position in CMU and realize the ADU logic by combinational circuit to keep the result of ADU within the same clock of context which can reduce the latency to zero clock cycle between CMU and ADU. We show that the proposed EDU architecture attains a throughput of 68.66–232.14 Mbps for a single decoding core depending on compression ratios, and consumes 95.79 mW based on SMIC 0.13 um technology. In comparison with the state-of-the-art decoders the proposed EDU architecture provides consistent reconstruction performance with software decoder and comparable throughput, memory and power consumption.

Achievable Moderate Deviations Asymptotics for Streaming Compression of Correlated Sources

Motivated by streaming multi-view video coding and wireless sensor networks, we consider the problem of blockwise streaming compression of a pair of correlated sources, which we term streaming Slepian-Wolf coding. We study the moderate deviations regime in which the rate pairs of a sequence of codes converge, along a straight line, to various points on the boundary of the Slepian-Wolf region at a speed slower than the inverse square root of the blocklength $n$, while the error probability decays subexponentially fast in $n$. Our main result focuses on directions of approaches to corner points of the Slepian-Wolf region. It states that for each correlated source and all corner points, there exists a non-empty subset of directions of approaches such that the moderate deviations constant (the constant of proportionality for the subexponential decay of the error probability) is enhanced (over the non-streaming case) by at least a factor of $T$, the block delay of decoding source block pairs. We specialize our main result to the setting of streaming lossless source coding and generalize this result to the setting where we have different delay requirements for each of the two source blocks. The proof of our main result involves the use of various analytical tools and amalgamates several ideas from the recent information-theoretic streaming literature. We adapt the so-called truncated memory encoding idea from Draper and Khisti (2011) and Lee, Tan, and Khisti (2016) to ensure that the effect of error accumulation is nullified in the limit of large blocklengths. We also adapt the use of the so-called minimum weighted empirical suffix entropy decoder which was used by Draper, Chang, and Sahai (2014) to derive achievable error exponents for symbolwise streaming Slepian-Wolf coding.

A Variable-Clock-Cycle-Path VLSI Design of Binary Arithmetic Decoder for H.265/HEVC

The next-generation 8K ultra-high-definition video format involves an extremely high bit rate, which imposes a high throughput requirement on the entropy decoder component of a video decoder. Context adaptive binary arithmetic coding (CABAC) is the entropy coding tool in the latest video coding standards including H.265/High Efficiency Video Coding and H.264/Advanced Video Coding. Due to critical data dependencies at the algorithm level, a CABAC decoder is difficult to be accelerated by simply leveraging parallelism and pipelining. This letter presents a new very-large-scale integration arithmetic decoder, which is the most critical bottleneck in CABAC decoding. Our design features a variable-clock-cycle-path architecture that exploits the differences in critical path delay and in probability of occurrence between various types of binary symbols (bins). The proposed design also incorporates a novel data-forwarding technique (rLPS forwarding) and a fast path-selection technique (coarse bin type decision), and is enhanced with the capability of processing additional bypass bins. As a result, its maximum throughput achieves 1010 Mbins/s in 90-nm CMOS, when decoding 0.96 bin per clock cycle at a maximum clock rate of 1053 MHz, which outperforms previous works by 19.1%.

Architecture for parallel marker-free variable length streams decoding

Due to throughput requirements above 1 gigapixel/sec for the real-time compression of modern image and video data streams, parallelism for encoding and decoding is inevitable. To achieve parallel decoding, a well-established technique is to insert markers into the variable length code (VLC) stream. By locating markers, it is then possible to extract the sub-streams that are, in turn, decoded in parallel. The use of markers adversely affects compression especially when a high degree of parallelism is required. In this paper, we propose an architecture of a marker-free parallel decoding approach of VLC streams. Instead of multiple local entropy decoders, the proposed architecture is based on using a single parallel entropy decoder in conjunction with a novel format to construct the VLC stream. The approach runs at high clock rates supporting parallelism to a high number of decoders. A synthesized clock frequency well above 110 MHz is achieved for up to 20 decoders on a medium-sized FPGA.

GHEVC: An Efficient HEVC Decoder for Graphics Processing Units

The high compression efficiency that is provided by the high efficiency video coding (HEVC) standard comes at the cost of a significant increase of the computational load at the decoder. Such an increased burden is a limiting factor to accomplish real-time decoding, specially for high definition video sequences (e.g., Ultra HD 4K). In this scenario, a highly parallel HEVC decoder for the state-of-the-art graphics processor units (GPUs) is presented, i.e., GHEVC. Contrasting to our previous contributions, the data-parallel GHEVC decoder integrates the whole decompression pipeline (except for the entropy decoding), both for intra- and interframes. Furthermore, its processing efficiency was highly optimized by keeping the decompressed frames in the GPU memory for subsequent inter frame prediction. The proposed GHEVC decoder is fully compliant with the HEVC standard, where explicit synchronization points ensure the correct HEVC module execution order. Moreover, the GPU-based HEVC decoder is experimentally evaluated for different GPU devices, an extensive range of recommended HEVC configurations and video sequences, where an average frame rate of 145, 318, and 605 frames per second for Ultra HD 4K, WQXGA, and Full HD, respectively, was obtained in the Random Access configuration with the NVIDIA GeForce GTX TITAN X GPU.

High throughput entropy decoder design for H.265/HEVC

The H.265/high efficiency video coding (HEVC) standard employs context-based adaptive binary arithmetic coding (CABAC) as a single entropy coding method. Despite the high coding efficiency of CABAC, its context modeling process limits the throughput and prevents effective parallelization, particularly at the decoder. In this paper, we design a new joint rate distortion-decoding complexity (RDDC) cost function to improve the throughput performance at the H.265/HEVC decoder side. The proposed RDDC cost function includes the complexity term based on a newly designed complexity model using the linear regression. Experimental results show that the proposed method reduces the number of context-coded bins up to 19.8 % without significant coding loss.

Maximum-Entropy Inference with a Programmable Annealer.

Optimisation problems typically involve finding the ground state (i.e. the minimum energy configuration) of a cost function with respect to many variables. If the variables are corrupted by noise then this maximises the likelihood that the solution is correct. The maximum entropy solution on the other hand takes the form of a Boltzmann distribution over the ground and excited states of the cost function to correct for noise. Here we use a programmable annealer for the information decoding problem which we simulate as a random Ising model in a field. We show experimentally that finite temperature maximum entropy decoding can give slightly better bit-error-rates than the maximum likelihood approach, confirming that useful information can be extracted from the excited states of the annealer. Furthermore we introduce a bit-by-bit analytical method which is agnostic to the specific application and use it to show that the annealer samples from a highly Boltzmann-like distribution. Machines of this kind are therefore candidates for use in a variety of machine learning applications which exploit maximum entropy inference, including language processing and image recognition.

Programming models and applications for multicores and manycores

Programming models and applications for multicores and manycores

Efficient layout data compression algorithm and its low-complexity, high-performance hardware decoder implementation for multiple electron-beam direct-write systems

A lossless electron-beam layout (EBL) data compression algorithm, LineDiff Entropy v2.0, and its low-complexity, high-performance hardware decoder for multiple electron-beam direct-write lithography systems are proposed. The algorithm compares consecutive data scanlines and encodes the data based on the change/no-change of pixel values and the lengths of pixel sequences. Then, the compaction steps of data omission, merging, and encoding of consecutive long identical scanlines are applied. Unique short codes are assigned to data with high occurrence frequency. The hardware decoder is designed as three circuit blocks that perform entropy decoding, decompaction, and EBL data generation through parallel outputs. The results demonstrate that our algorithm can achieve excellent compression performance and that the hardware decoder can decompress data at very high data rates.

A Deeply Pipelined CABAC Decoder for HEVC Supporting Level 6.2 High-Tier Applications

High Efficiency Video Coding (HEVC) is the latest video coding standard that specifies video resolutions up to 8K ultra-high definition (UHD) at 120 frames/s to support the next decade of video applications. This results in high-throughput requirements for the context-adaptive binary arithmetic coding (CABAC) entropy decoder, which was already a well-known bottleneck in H.264/AVC. To address the throughput challenges, several modifications were made to CABAC during the standardization of HEVC. This paper leverages these improvements in the design of a high-throughput HEVC CABAC decoder. It also supports the high-level parallel processing tools introduced by HEVC, including tile and wavefront parallel processing. The proposed design uses a deeply pipelined architecture to achieve a high clock rate. Additional techniques such as the state prefetch logic, latched-based context memory, and separate finite state machines are applied to minimize stall cycles, while multibypass-bin decoding is used to further increase the throughput. The design is implemented in an International Business Machines 45-nm silicon on insulator process. After place and route, its operating frequency reaches 1.6 GHz. The corresponding throughputs achieve up to 1696 and 2314 Mbin/s under common and theoretical worst-case test conditions, respectively. The results show that the design is sufficient to decode in real-time high-tier video bitstreams at level 6.2 (8K UHD at 120 frames/s), or main-tier bitstreams at level 5.1 (4K UHD at 60 frames/s) for applications requiring subframe latency, such as video conferencing.