Enhancement-mode Transistors Research Articles

Device and material investigations of GaN enhancement-mode transistors for Venus and harsh environments

This Letter reports the device and material investigations of enhancement-mode p-GaN-gate AlGaN/GaN high electron mobility transistors (HEMTs) for Venus exploration and other harsh environment applications. The GaN transistor in this work was subjected to prolonged exposure (11 days) in a simulated Venus environment (460 °C, 94 bar, complete chemical environment including CO2/N2/SO2). The mechanisms affecting the transistor performance and structural integrity in harsh environment were analyzed using a variety of experimental, simulation, and modeling techniques, including in situ electrical measurement (e.g., burn-in) and advanced microscopy (e.g., structural deformation). Through transistor, Transmission Line Method (TLM), and Hall-effect measurements vs temperature, it is revealed that the mobility decrease is the primary cause of reduction of on-state performance of this GaN transistor at high temperature. Material analysis of the device under test (DUT) confirmed the absence of foreign elements from the Venus atmosphere. No inter-diffusion of the elements (including the gate metal) was observed. The insights of this work are broadly applicable to the future design, fabrication, and deployment of robust III-N devices for harsh environment operation.

Eutectogels as a Semisolid Electrolyte for Organic Electrochemical Transistors.

Organic electrochemical transistors (OECTs) are signal transducers offering high amplification, which makes them particularly advantageous for detecting weak biological signals. While OECTs typically operate with aqueous electrolytes, those employing solid-like gels as the dielectric layer can be excellent candidates for constructing wearable electrophysiology probes. Despite their potential, the impact of the gel electrolyte type and composition on the operation of the OECT and the associated device design considerations for optimal performance with a chosen electrolyte have remained ambiguous. In this work, we investigate the influence of three types of gel electrolytes-hydrogels, eutectogels, and iongels, each with varying compositions on the performance of OECTs. Our findings highlight the superiority of the eutectogel electrolyte, which comprises poly(glycerol 1,3-diglycerolate diacrylate) as the polymer matrix and choline chloride in combination with 1,3-propanediol deep eutectic solvent as the ionic component. This eutectogel electrolyte outperforms hydrogel and iongel counterparts of equivalent dimensions, yielding the most favorable transient and steady-state performance for both p-type depletion and p-type/n-type enhancement mode transistors gated with silver/silver chloride (Ag/AgCl). Furthermore, the eutectogel-integrated enhancement mode OECTs exhibit exceptional operational stability, reflected in the absence of signal-to-noise ratio (SNR) variation in the simulated electrocardiogram (ECG) recordings conducted continuously over a period of 5 h, as well as daily measurements spanning 30 days. Eutectogel-based OECTs also exhibit higher ECG signal amplitudes and SNR than their counterparts, utilizing the commercially available hydrogel, which is the most common electrolyte for cutaneous electrodes. These findings underscore the potential of eutectogels as a semisolid electrolyte for OECTs, particularly in applications demanding robust and prolonged physiological signal monitoring.

Dual-Analyte Sensing with a Molecularly Imprinted Polymer Based on Enhancement-Mode Organic Electrochemical Transistors.

Novel enhancement-mode organic electrochemical transistors (OECTs) have been prepared by poly(3, 4-ethylenedioxythiophene)-poly(styrenesulfonate) de-doped polyethylenimine on the multi-walled carbon nanotube-modified viscose yarn. The fabricated devices exhibit low power consumption with a high transconductance of 6.7 mS, rapid response time < 2 s, and excellent cyclic stability. In addition, the device has washing durability and bending and long-term stability suitable for wearable applications. Biosensors based on enhancement-mode OECTs for the selective detection of adrenaline and uric acid (UA) are developed by using molecularly imprinted polymer (MIP)-functionalized gate electrodes. The detection limits of adrenaline and UA analysis are as low as 1 pM, with the linear ranges of 0.5 pM to 10 μM and 1 pM to 1 mM, respectively. Moreover, the sensor based on enhancement-mode transistors can efficiently amplify the current signals according to the modulation of the gate voltage. The MIP-modified biosensor has high selectivity in the presence of interferents and desirable reproducibility. Additionally, due to the wearable nature of the developed biosensor, this sensing tool has the capability of being integrated with fabrics. Therefore, it has successfully been applied in textiles for the determination of adrenaline and UA in artificial urine samples. The excellent recoveries and rsds are 90.22-109.05% and 3.97-6.94%, respectively. Ultimately, these sensitive, low-power, wearable, and dual-analyte sensors help to develop non-laboratory tools for early disease diagnosis and clinical research.

State-of-the-Art β-Ga2O3 Field-Effect Transistors for Power Electronics.

Due to the emergence of electric vehicles, power electronics have become the new focal point of research. Compared to commercialized semiconductors, such as Si, GaN, and SiC, power devices based on β-Ga2O3 are capable of handling high voltages in smaller dimensions and with higher efficiencies, because of the ultrawide bandgap (4.9 eV) and large breakdown electric field (8 MV cm–1). Furthermore, the β-Ga2O3 bulk crystals can be synthesized by the relatively low-cost melt growth methods, making the single-crystal substrates and epitaxial layers readily accessible for fabricating high-performance power devices. In this article, we first provide a comprehensive review on the material properties, crystal growth, and deposition methods of β-Ga2O3, and then focus on the state-of-the-art depletion mode, enhancement mode, and nanomembrane field-effect transistors (FETs) based on β-Ga2O3 for high-power switching and high-frequency amplification applications. In the meantime, device-level approaches to cope with the two main issues of β-Ga2O3, namely, the lack of p-type doping and the relatively low thermal conductivity, will be discussed and compared.

Selective sublimation of GaN and regrowth of AlGaN to co-integrate enhancement mode and depletion mode high electron mobility transistors

In the present study, the selective sublimation of the p-GaN cap layer of Al(Ga)N/GaN HEMTs is developed to replace the commonly used dry etching with no risk of damage in the barrier layer in order to fabricate enhanced mode transistors. Thanks to this approach, enhancement-mode transistors are fabricated with a threshold voltage between 0 V and +1.5 V depending on the barrier layer aluminum molar fraction and thickness. Furthermore, we show the benefit of the combination of selective sublimation with the regrowth of AlGaN to reduce access resistance in these transistors which can be co-integrated with depletion-mode devices fabricated in the same process in areas where p-GaN has been totally evaporated.

Comparison of GaN Enhancement Mode Transistor Performance With Integrated and External Driver

GaN components allow to reduce power losses as the lower specific on-resistance and higher switching speeds reduce both the conduction and switching loss. However, parasitics in the gate loop cause ringing which endangers the component. To counteract these problems the switching speed is lowered renouncing part of the components superior performance. A possible way to avoid gate loop parasitics and make circuit design less challenging is integrating the driver in the same package with the GaN transistor. In this paper the performance of an integrated driver with enhancement mode GaN half-bridge that is monolithically integrated using IMEC GaN-on-SOI will be tested in a synchronous boost converter setup. Converter efficiency and switching waveforms will be reported together with a comparison to a GaN half-bridge with external drivers. The converter is tested at input voltages up to 50 V and powers up to 100 W. Package temperature measurements are included to estimate the influence of the temperature dependent on-resistance on the results. At the end of the paper, a sensitivity analysis is conducted to quantify the behaviour of the losses in function of different input parameters including a measurement at switching frequencies up to 1MHz.

GaN-on-Si: Monolithically Integrated All-GaN Drivers for High-Voltage DC-DC Power Conversion

This paper presents a novel integrated half-bridge driver architecture using GaN-on-Si process for high-speed and high-voltage DC-DC converters. The entire circuit includes only enhancement mode (E-mode) and depletion-mode (D-mode) GaN transistors. The high-side driver circuit adopts the E-stacked E/D-mode (EED) architecture, which can directly drive the gate of the high-side transistor with a low-voltage signal without using an additional level shifter, which simplifies the design and reduces propagation delay. In addition, the low-side power transistor is driven by stacking two D/E-mode devices. This architecture separates the high-side pulse from the low-side drive signal to prevent false triggering of the low-side driver. The designed fully integrated GaN driver can output a high-voltage pulse wave with an operating frequency greater than 1 MHz when the input voltage is greater than 200 V. The rise and fall times of the high-voltage pulse wave operating at a peak voltage of 200 V are 54.4 ns and 57.6 ns, respectively. The experimental results show that the circuit can effectively drive the half-bridge circuit and be applied to a buck converter. The designed buck converter can deliver up to 20.5 W of output power, and the maximum efficiency achieves 90.7%.

Normally-Off p-GaN Gated AlGaN/GaN MIS-HEMTs with ALD-Grown Al2O3/AlN Composite Gate Insulator.

A metal–insulator–semiconductor p-type GaN gate high-electron-mobility transistor (MIS-HEMT) with an Al2O3/AlN gate insulator layer deposited through atomic layer deposition was investigated. A favorable interface was observed between the selected insulator, atomic layer deposition–grown AlN, and GaN. A conventional p-type enhancement-mode GaN device without an Al2O3/AlN layer, known as a Schottky gate (SG) p-GaN HEMT, was also fabricated for comparison. Because of the presence of the Al2O3/AlN layer, the gate leakage and threshold voltage of the MIS-HEMT improved more than those of the SG-HEMT did. Additionally, a high turn-on voltage was obtained. The MIS-HEMT was shown to be reliable with a long lifetime. Hence, growing a high-quality Al2O3/AlN layer in an HEMT can help realize a high-performance enhancement-mode transistor with high stability, a large gate swing region, and high reliability.

Correlation between sidewall surface states and off-state breakdown voltage of AlGaN/GaN HFETs

Correlation between the sidewall surface states and off-state breakdown voltage of AlGaN/GaN heterojunction field effect transistors (HFETs) is investigated for the first time. HFETs explored in this work were realized on a variety of isolation features including conventional mesa, non-slanted fin, and slanted fin. The output and transfer characteristics of the devices from all categories of the fabricated AlGaN/GaN HFETs were studied, and a link between the separation of isolation feature sidewalls in the drain access region and the breakdown voltage was observed. Simulation results showed that by shrinking the width of the isolation feature geometry, the peak of the electric field at the drain edge of the gate is reduced as a result of tailoring its profile when a more resistive path is imposed on the drain access region. While HFETs realized on fins of smaller width benefit more from the depleting effect of acceptor sidewall surface states and consequently a higher off-state breakdown voltage, they suffer from a lower current density in the on-state. The slanted fin isolation feature geometry that we proposed here, while maintaining high breakdown voltage in the off-state, reduces the resistance in the on-state, which is represented by its highest Baliga's figure of merit among the three categories of isolation feature geometries. The proposed solution for achieving an improvement to the off-state breakdown voltage of AlGaN/GaN HFETs relies on a technology that has already been explored as a successful alternative for the realization of enhancement-mode transistors (i.e., with positive threshold voltage).

Monolithically integrated voltage-controlled MOSFET-LED device based on a GaN-on-silicon LED epitaxial wafer.

We report a novel monolithically integrated voltage-controlled metal-oxide-semiconductor field effect transistor (MOSFET)-LED device based on a GaN-on-silicon LED epitaxial wafer. An N-channel enhancement mode MOSFET and an InGaN/GaN multiple-quantum-well (MQW) thin-film LED featured with a suspended membrane are in series connection to constitute the monolithically integrated device without external metal interconnection. A recessed gate structure and AlGaN channel are innovatively adopted to realize an enhancement mode transistor. The fabrication of the MOSFET-LED includes no additional ion implantation or epitaxial growth compared with that of a common MQW LED, which greatly simplifies the device structure and production processes. The measured turn-on voltage of the LED is approximately 4 V, and the threshold voltage of the MOSFET is extrapolated as 5.2 V. The results demonstrate relatively good dimming and switching capacities of the integrated MOSFET-LED. This integration scheme also has potential to achieve a large-scale optoelectronic integrated circuit.

(Invited) the Outlook for Al-Rich AlGaN Transistors

High critical electric field (EC) and a large saturation velocity in ultra-wide bandgap transistors (UWBG) such as Al-rich AlGaN and ß-Ga2O3 is stimulating research into these devices [1,2]. This research is aimed at producing devices that may one day excel in power switching [3] and RF applications [4]. Figure-of-merit (FOM) analysis supports the possibility that Al-rich AlGaN transistors will outperform other WBG and UWBG transistors [5,6]. In spite of this promise, the UWBG devices do not yet perform well enough reach the promise evidenced by the FOM analysis. The favorable resolution of several important issues may be the key to broad acceptance of Al-rich AlGaN transistors. Until that time, Al-rich AlGaN transistors will begin to find utility in less mainstream uses. Recent developments are encouraging for the acceptance of Al-rich AlGaN in harsh environments.This talk will describe multiple research efforts to develop Al-rich AlGaN into the material of choice for next-generation power electronics applications and compare these research results to other WBG transistors where appropriate. These transistors generally benefit from the materials and fabrication similarity to AlGaN/GaN. They are grown epitaxially in the same metal organic chemical vapor deposition reactors and on mostly the same substrates. They will also benefit from similar fabrication infrastructure that is in place for AlGaN/GaN. Likewise, the AlGaN alloys support a wide diversity of device types. Depending on the targeted application, the AlGaN transistors may be depletion-mode (normally-on) or enhancement-mode (normally-off) transistors. Diversity in device types also includes various types of device designs that have been investigated, including metal-semiconductor field effect transistors, high electron mobility transistors (HEMTs), metal-insulator-semiconductor transistors, metal-oxide transistors, and polarization doped transistors.We will also describe the progress in maturing this transistor technology along a number of fronts. They are improving towards high current density at a rapid rate through efforts to improve the mobility, efforts to improve the Ohmic contacts, and by means of aggressively scaling the device dimensions. The particular strengths of the Al-rich AlGaN transistor include high electric field at breakdown, which is already more than 2-times that of GaN, the high ION/IOFF ratio in the transistor, now exceeding 109 in multiple devices, and in their high temperature operation with multiple reports in the 300-500°C range. A recent comparison of an Al0.85Ga0.15N/Al0.7Ga0.3N HEMT against AlGaN/GaN showed a superior ION/IOFF ratio at 500°C and also shows a favorable extrapolation to the 500-800°C temperature range for Al0.7Ga0.3N but not for GaN [7]. Such results are beginning to suggest that AlGaN may one day become the preferred transistor for operation at extreme temperatures. Details regarding ongoing work to optimize device performance for Al-rich AlGaN transistors will be presented in the talk.[1] A.G. Baca et al., J. Vac. Science and Technology, 40, 1600501 (2020).[2] M. Higashiwaki and G. H. Jessen, Appl. Phys. Lett. 112, 060401 (2018).[3] R. J. Kaplar et al., J. Solid-State Sci. Technol., 6, Q3061 (2017).[4] R. J. Kaplar et al., Proc. GOMAC, Albuquerque, NM, USA (2019), pp. 587-591.[5] Coltrin et al., J. Solid-State Sci. Technol., 6, S3114 (2017).[6] S. Bajaj et al., Appl. Phys. Lett. 105, 263503 (2014).[7] P. H. Carey et al., J. Electron Devices Society, 7, 444 (2019).This work was supported by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. The views expressed in the presentation do not necessarily represent the views of the U.S. Department of Energy or the United States Government.

Charge trap layer enabled positive tunable Vfb in β -Ga2O3 gate stacks for enhancement mode transistors

β-Ga2O3 based enhancement mode transistor designs are critical for the realization of low loss, high efficiency next generation power devices with rudimentary driving circuits. A large positive flatband voltage (Vfb) of 10.6 V in β-Ga2O3 metal-oxide-semiconductor capacitors, with the ability to fine-tune it between 3.5 V and 10.6 V, using a polycrystalline AlN charge trap layer has been demonstrated. This can enable enhancement mode operation over a wide doping range. An excellent Vfb retention of ∼97% for 104 s at 55 °C was exhibited by the gate stacks after charge trapping, hence reducing the requirement of frequent charge injection cycles. In addition, low gate leakage current density (Jg) for high negative gate voltages (Vg ∼−60 V) indicates the potential of this gate stack to enable superior breakdown characteristics in enhancement mode transistors.

Channel mobility and contact resistance in scaled ZnO thin-film transistors

ZnO thin-film transistors (TFTs) with scaled channel lengths of 10 μm, 5 μm, 4 μm, and 2 μm exhibit increasing intrinsic channel electron mobility at a gate bias of 10 V (15 V) from 0.782 cm2/Vs (0.83 cm2/Vs) in the 10 μm channel length TFT to 8.9 cm2/Vs (19.04 cm2/Vs) for the channel length scaled down to 2 μm. Current-voltage measurements indicate an n-type channel enhancement mode transistor operation, with threshold voltages in the range of 8.4 V to 5.3 V, maximum drain currents of 41 μA/μm, 96 μA/μm, 193 μA/μm, and 214 μA/μm at a gate bias of 10 V, and breakdown voltages of 80 V, 70 V, 62 V, and 59 V with respect to channel lengths of 10 μm, 5 μm, 4 μm, and 2 μm. The channel electron mobility (excluding contact resistance) is extracted by the transmission line method (TLM) from the effective electron mobility (including contact resistance). The contact sheet resistance of4.6×105Ω/sq extracted from the measurements, which is 3.5× larger than the contact sheet resistance of 1.3×105Ω/sq obtained from the DFT calculation and the 1D self-consistent Poisson-Shrödinger simulation, largely limits the drive current in the scaled ZnO TFTs.

Normally-off AlN/β-Ga2O3 field-effect transistors using polarization-induced doping

III-nitrides and beta-phase gallium oxide (β-Ga2O3) are currently two intensively investigated wide bandgap semiconductor materials for power electronics. Due to the relatively low lattice mismatch between the two material systems and the availability of bulk AlN, GaN and β-Ga2O3 substrates, epitaxial growth of III-nitrides on β-Ga2O3 or vice versa has been realized. However, the design of power devices by integrating the two material systems is still lacking. Here we numerically investigate an AlN/β-Ga2O3 heterostructure by taking advantage of polarization-induced doping to realize high-performance enhancement-mode transistors. Induced by polarization effects at the AlN/β-Ga2O3 interface, a 2-dimensional electron gas concentration can reach up to 8.1 × 1019 cm−3 in the channel. On top of the channel, a p-GaN gate was introduced and eventually a normally-off AlN/β-Ga2O3 field-effect transistor with tunable positive threshold voltages was realized. Furthermore, we inserted an unintentionally doped GaN back barrier layer to suppress the drain leakage current. Eventually, the transfer and output characteristics of the proposed device with different structural parameters were further investigated and analyzed in the pursuit of high-performance III-nitrides/Ga2O3-based power devices.

Gate Conduction Mechanisms and Lifetime Modeling of p-Gate AlGaN/GaN High-Electron-Mobility Transistors

The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole–Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN “p-i-n” diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/ p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at ${t}_{\textsf {1}\%}=\textsf {10}$ years.

Multichannel ZnO nanowire field effect transistors by lift-off process

This paper describes a new, low-cost, top-down fabrication process, which makes it possible to define nanowire field effect transistor arrays with different numbers of nanowires simultaneously and systematically comparing their electrical performance. The main feature of this process is a developed bilayer photoresist pattern with a retrograde profile, which enables the modification of the nanowire in width, length, height and the number of transistor channels. The approach is compatible with low-cost manufacture without electron beam lithography, and benefits from process temperatures below 190 °C. Process reliability has been investigated by scanning electron microscopy, transmission electron microscopy and atomic force microscopy. Electrical measurements demonstrate enhancement mode transistors, which show a scalable correlation between the number of nanowires and the electrical characteristics. Devices with 100 nanowires exhibit the best performance with a high field effect mobility of 11.0 cm2 Vs–1, on/off current ratio of 3.97 × 107 and subthreshold swing of 0.66 V dec–1.

Natural‐air‐cooled 5 kVA single‐phase GaN inverter with paralleled multilayer PCB magnetics

In this study, a systematic approach to the design and development of a high-efficiency, natural-air-cooled, single-phase inverter with a multilayer high-current printed-circuit board (PCB) magnetics is presented. The size and efficiency of inverters implemented with the silicon transistor technology have almost reached a certain limit. The use of wide bandgap power semiconductors, such as the silicon carbide metal–oxide–semiconductor field-effect transistor and the gallium nitride (GaN) enhancement-mode (e-mode) transistor not only pushes further the efficiency limits, but also shrinks the inverter size. A new approach is proposed here in order to obtain a high-efficiency inverter which relies basically upon the derivation of analytical expressions for the inverter losses as a function of the inverter modulation index, for the optimum transistor and highest switching frequency pair selection, and the design of the output filter based on a paralleled, multilayer PCB magnetics. In the developed 5 kVA single-phase full-bridge inverter, GaN e-mode transistors are used to minimise the inverter losses and to decrease the cooling requirement, and size of the system. The proposed systematic design approach has been verified on the implemented 5 kVA, 50 kHz, naturally-cooled GaN inverter, with a power density of 2.7 W/cm 3 (44.3 W/inch 3 ), and a full-load efficiency of 98%.

Ultra-low rate dry etching conditions for fabricating normally-off field effect transistors on AlGaN/GaN heterostructures

Enhancement-mode transistors with uniform turn-on threshold voltage (Vth) can be achieved using low damage and low rate gate recess etching techniques. In this work, dry etching conditions for a AlGaN/GaN heterostructure with an ultra-low etching rate of 1.5 nm/min were demonstrated and we succeeded the possibility to achieve a low etch rate of an AlGaN/GaN heterostructure in a Cl2/BCl3 plasma using inductively coupled plasma (ICP). The etching development was successfully implemented in the achievement of a normally-off GaN/AlGaN based transistor. The optimal recess depth was determined after fabrication of various devices with different recess depth values and with various dry etching conditions and after examining the performances of fabricated devices various conditions, and determining the dependence of recess time. The optimized etching condition resulted in low damage and smooth morphology of the etched AlGaN/GaN surfaces. Fine control of the depth of the gate region recess was achieved for the AlGaN/GaN heterostructure without any etch-stop layer, and validated for the fabrication of field effect transistors (FETs) using conventional processes. The fabricated normally-off Al2O3/AlGaN/GaN MOSFETs delivered a high positive Vth of +5.64 V with a low off-state leakage current of ∼10−7 A/mm and lower current collapse.

The Positive Effects of Hydrophobic Fluoropolymers on the Electrical Properties of MoS2 Transistors

We report the improvement of the electrical performance of field effect transistors (FETs) fabricated on monolayer chemical vapor deposited (CVD) MoS2, by applying an interacting fluoropolymer capping layer (Teflon-AF). The electrical characterizations of more than 60 FETs, after applying Teflon-AF cap, show significant improvement of the device properties and reduced device to device variation. The improvement includes: 50% reduction of the average gate hysteresis, 30% reduction of the subthreshold swing and about an order of magnitude increase of the current on-off ratio. These favorable changes in device performance are attributed to the reduced exposure of MoS2 channels to the adsorbates in the ambient which can be explained by the polar nature of Teflon-AF cap. A positive shift in the threshold voltage of all the measured FETs is observed, which translates to the more desirable enhancement mode transistor characteristics.

Control of threshold voltage in E-mode and D-mode GaN-on-Si metal-insulator-semiconductor heterostructure field effect transistors by in-situ fluorine doping of atomic layer deposition Al2O3 gate dielectrics

We report the modification and control of threshold voltage in enhancement and depletion mode AlGaN/GaN metal-insulator-semiconductor heterostructure field effect transistors through the use of in-situ fluorine doping of atomic layer deposition Al2O3. Uniform distribution of F ions throughout the oxide thickness are achievable, with a doping level of up to 5.5 × 1019 cm−3 as quantified by secondary ion mass spectrometry. This fluorine doping level reduces capacitive hysteretic effects when exploited in GaN metal-oxide-semiconductor capacitors. The fluorine doping and forming gas anneal also induces an average positive threshold voltage shift of between 0.75 and 1.36 V in both enhancement mode and depletion mode GaN-based transistors compared with the undoped gate oxide via a reduction of positive fixed charge in the gate oxide from +4.67 × 1012 cm−2 to −6.60 × 1012 cm−2. The application of this process in GaN based power transistors advances the realisation of normally off, high power, high speed devices.