Emitter Function Logic Research Articles

The new super-high-speed digital circuit based on linear and-or gates

The paper reveals the relation between the linear AND-OR gate and the emitter function logic. With theoretic calculation and PSPICE simulation, the paper proves that the linear AND-OR gates can work at super-high-speed and can be multi-cascaded. On the basis of analyzing the high-speed switch units which coordinate with linear AND-OR gates, two kinds of emitter coupled logic circuits are designed. The paper also discusses the design principles of super-high-speed digital circuits, and some examples of combinational and sequential circuits using linear AND-OR gate are given.

D-flip-flop with a programmable delay with power consumption for implementation in smart sensors

Abstract The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

A mixed EFL I2L digital telecommunication integrated circuit

A bipolar digital telecommunications circuit has been designed in the OXIL technology as part of a VLSI upgrade of an existing digital switching circuit. The chip is unique in its exploitation of the OXIL oxide isolated process which allows both high gain "up" and "down" devices used for I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L and EFL (emitter function logic), respectively. This allowed the circuit designers to tailor power consumption, circuit speed, and gate density as needed. In particular, the high speed properties of EFL were utilized in the control section to provide accurate timing signals and satisfy tight propagation delay requirements in the register section. I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L, because of its greater density and low power, was used in the gate intensive register sections. Another novel feature of this device was the treatment of bus lines (up to 250 fanout) such as clock, clear, etc., in the I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L sections. The common multiline I <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> L drive problem has been overcome here by using high drive translators from EFL circuitry and a single pullup resistor per bus line to provide switched currents to all gates on that line.

A mixed EFL/I/sup 2/L digital telecommunication integrated circuit

A bipolar integrated circuit has been designed as part of a VLSI upgrade of an existing digital switching circuit. The chip exploits the OXIL (oxide isolated) process which makes it possible to use both high-gain `up' and `down' devices, for I/SUP 2/L (integrated injection logic) and EFL (emitter function logic) respectively. This allowed the circuit designers to tailor power consumption, circuit speed, and gate density as needed. In particular, the high-speed properties of EFL were utilized in the control section to provide accurate timing signals and satisfy tight propagation delay requirements in the register section. I/SUP 2/L, because of its greater density and low power, was used in the gate-intensive register sections. Another novel feature is the treatment of bus lines (up to 250 fanout) such as clock, clear, etc., in the I/SUP 2/L sections. The common multiline I/SUP 2/L drive problem has been overcome by using high-drive translators from EFL circuitry and a single pullup resistor per bus line to provide switched currents to all gates on that line.

High speed current mode logic for LSI

A high speed/low power logic family is described which combines the best features of current mode logic (CML), emitter-coupled logic (ECL), and emitter function logic (EFL). This is combined with a low voltage-current source, using the principle of current imaging, to provide three levels of series gating with reduced supply voltages. With relatively slow transistors ( f_1 =500 MHz) circuit structures have been fabricated which provide several logic levels with a total delay of 2 ns and total power dissipation of 2 mW per circuit structure. The paper also describes the implementation of ROM's, RAM's, and PLA's using the principle of current steering. An analysis is given for circuit operation with variation in supply voltage and temperature. Three fabricated LSI chips are described with an average of 1000 equivalent gates per chip.

A low-power, bipolar, two's complement serial pipeline multiplier chip

A 4-bit, general-purpose, two's complement serial pipeline multiplier chip has been designed and fabricated in the bipolar GIMIC-O process. The chip can provide the following functions in 24-pin dual-in-line packages: (1) two's complement/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial pipeline multiplier with programmable coefficients, (3) 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) overflow corrector. Packages can be cascaded to provide functions of length greater than 4 bits. Nonsaturating circuit techniques, emitter function logic combined with current-steering trees, are effectively utilized to make high-performance, low-power circuits using a simple bipolar technology. The multiplier circuitry is compatible at inputs and outputs with standard emitter coupled logic and uses a standard -5.2/spl plusmn/10 percent power supply. Fully programmable multiplication at clock rates greater than 20 MHz is achieved with a power consumption of 37.5 mW/bit.

Direct-coupled transistor-transistor logic: a new high-performance LSI gate family

The direct-coupled transistor-transistor logic (DCT/SUP 2/L) family consists of a multiple-emitter AND gate and a NOR gate similar to direct-coupled transistor logic (DCTL). High speed for low power is obtained by limiting the voltage swing and using a low voltage power supply of about 2 V. Using a conservative, standard Schottky process, the DCT/SUP 2/L NOR gate has a delay of about 1 ns for 4-mW gate power. A computer-aided analysis shows that this is faster than the basic gates of emitter function logic (EFL), emitter-coupled logic (ECL), or Schottky transistor-transistor logic (T/SUP 2/L) with the same process and gate power. A comparison of actual arithmetic logic units shows that Schottky DCT/SUP 2/L is smaller and faster than ECL and Schottky T/SUP 2/L. The higher speed and density of DCT/SUP 2/L makes it a better large-scale integration (LSI) concept than the other logic families.

Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers

Logic-in-memory (LIM) organization allows central processor functions of computing systems to be combined with memory in regular arrays. The cells of these arrays can themselves be constructed regularly and economically using similar two-level emitter-function logic (EFL) structures. The structure is a development of current-mode logic and it permits the large-scale integration (LSI) realization of three levels of logic with similar silicon area and power dissipation to a single conventional emitter-coupled logic (ECL) gate. It also permits the realization of a D latch in a single structure. The capability of the structure is demonstrated in examples of LIM data transfer and sorting arrays.

Plasma ions clean and etch integrated circuits : Electronics, June 7 (1973), p.

The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

Generating pulses with C-MOS flip-flops : F. J. Marlowe and J. P. Hasili. Electronics, June (1973),p.

The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

Fast buffer store has self-control : J. Stockton. Electron. Engng, June (1973), p. 55

The ultimate goal in integrated silicon smart sensors is the merge of the sensor, analog readout circuits and the digital circuits that are required for AD conversion and for driving of a sensor bus for direct computer interfacing on a single chip. The main problems in such devices are the compatibility between these units and the fabrication yield. Emitter-coupled logic (ECL) circuits will be shown to be the most tolerant to variations in a bipolar process. Extending the basic ECL circuit with a non-linear load enables the construction of logic elements with a flexible electronic programming of the delay per basic logic circuit at an almost constant delay-power consumption product. An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the tolerance to processing fluctuations with an acceptable die area consumption (245 × 332 μm2). These properties strongly attribute to the viability of having an integrated on-chip sensor bus.

Emitter function logic-logic family for LSI

A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.