Embedding Technology Research Articles

Investigation of electrical performance and mechanical reliability of device embedded power module

We investigate electrical properties and reliabilities of DC-DC converter module with the use of embedding technology. We designed and manufactured two kinds of DC-DC converter module as a means of verification for these characteristics. One is the surface mounted module with side-by-side structure for reference and another is the device embedded module. To evaluate time-domain simulation analysis accurately, we conducted accurate built circuit model of the DC-DC converter IC and extracted multi-port S-parameters models including multi-coupled wiring models primarily. As a result of time domain voltage waveform simulation using these accurate built circuit model and multi-port S-parameters, we verified that the device embedded power module is excellent in electrical characteristics of switching operation. We demonstrated in this study that miniaturization of approximately 25% for the module size and voltage noise improvement of approximately 50% compared with the surface mounted power module when applying device embedding technology. Furthermore we validated these electrical performances of the device embedded power module by using experimental measurement method. We evaluated mechanical and electrical reliabilities of the device embedded power module collaterally, in consequence mechanical and electrical reliabilities of the device embedded module holds the sufficient performances

Embedded Chip Technology: Technologies, Applications and Future Developments

Technology approaches for the embedding of active and passive components using printed circuit board materials and processing gained an increasingly high interest over the last years. The use of such technologies for industrial fabrication has attracted increasingly interest by manufacturers and commercial products have been released. The realization of embedded modules is quite a robust process for different applications. Several approaches for a laminate based embedding of components were developed and implement into the manufacturing. An overview and status of the different methods and their advantages for specific applications will be given. The process flow, yield and challenges of such technologies for miniaturized packages and modules will be presented briefly. By nature of the process, extremely flat packages can be realized. The routing of electrical contacts from the embedded components to the top and bottom side of the package allows the fabrication of highly versatile package layouts. The flatness and freedom in design makes these packages ideal candidates for package on package stacking. The main focus of the presentation will be the discussion of different applications. Single and multi-component packages will be presented. Extensive reliability testing of single die packages was done in order to compare different material sets for embedding, but also to compare the reliability of such embedded die packages with conventional packages. In addition, new process developments targeting the embedding of ultra-fine pitch dies, with pad pitches below 100 μm, will be shown. Manifold applications targeting e.g. medical and power electronic modules will be presented and their way of manufacturing will be described. Recent developments focus on the use of such embedding technologies for the integration of high-power modules e.g. for automotive applications (Hybrid and eCars). Beside the integration of semiconductors, to achieve miniaturization and high robustness of such modules, also the use of organic substrates as an alternative to currently used direct copper bonded (DCB) boards is of high interest. The need to handle high current and to realize an excellent thermal management are the main challenges for these modules. The concepts and first results of these latest developments will be presented in detail. Rozalia/Ron ok move from 2.5/3D to Passive 1-3-12.

Next Generation eWLB (Embedded Wafer Level BGA): Advanced 3D SiP Packaging Solution

Current and future demands of mobile/portable electronic systems in terms of performance, power consumption, reliable system at a reasonable price are met by developing advanced/appropriate silicon process technology, innovative packaging solutions with use of chip-package-system co-design, low cost materials, advanced assembly and reliable interconnect technologies. In this article packaging evolution for hand held application is discussed with special focus on next generation chip embedding technology called eWLB in detail. To meet the above said challenges eWLB was developed which offers additional space for routing higher I/O chips on top of Silicon chip area which is not possible in conventional WLP or WLB. It also offers comparatively better electrical, thermal and reliability performance at reduced cost with possibility to address more Moore [decreasing technology nodes with low-k dielectrics in SoC] and more than Moore [heterogeneous integration of chips with different wafer technology as SiP solution in multi die or 3D eWLB approaches]. Currently 1st generation eWLB technology is available in the industry with 200mm and 300mm carrier size. This paper will highlight some of the recent advancements in progress development and mechnical characterization in component level and board level reliaiblity of next generation eWLB technologies of double-side 3D eWLB. Standard JEDEC tests were carried out to investigate component level reliability and both destructive/non-destructive analysis was performed to investigate potential structural defects. Daisychain Test vehicles were prepared and also tested for drop and TcoB (Temperature on Board) reliaiblity in industry standard test conditions. There was significant improvement of characteristic lifetime with thined eWLB in TcoB performance because of its enhanced flexibility of package. And there was study of board level reliabiilty with underfill in SMT for large size eWLB packages. This paper will also present study of package warpage behavior with temperature profile as well as failure analysis with microsturctural observation for comprehensive understanding of mechanical behavior of next generation eWLBs.

Active and Passive Devices Embedded in Laminate-Based Multilayer Board

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.

Customization of Curriculum Materials in Science: Motives, Challenges, and Opportunities

Exemplary science instructors use inquiry to tailor content to student’s learning needs; traditional textbooks treat science as a set of facts and a rigid curriculum. Publishers now allow instructors to compile pieces of published and/or self-authored text to make custom textbooks. This brings numerous advantages, including the ability to produce smaller, cheaper text and added flexibility on the teaching models used. Moreover, the internet allows instructors to decentralize textbooks through easy access to educational objects such as audiovisual simulations, individual textbook chapters, and scholarly research articles. However, these new opportunities bring with them new problems. With educational materials easy to access, manipulate and duplicate, it is necessary to define intellectual property boundaries, and the need to secure documents against unlawful copying and use is paramount. Engineers are developing and enhancing information embedding technologies, including steganography, cryptography, watermarking, and fingerprinting, to label and protect intellectual property. While these are showing their utility in securing information, hackers continue to find loop holes in these protection schemes, forcing engineers to constantly assess the algorithms to make them as secure as possible. As newer technologies rise, people still question whether custom publishing is desirable. Many instructors see the process as complex, costly, and substandard in comparison to using traditional text. Publishing companies are working to improve attitudes through advertising. What lacks is peer reviewed evidence showing that custom publishing improves learning. Studies exploring the effect of custom course materials on student attitude and learning outcomes are a necessary next step.

Realization of Power Modules by Chip Embedding Technology

The continuous miniaturization of silicon dies and the need for a further package size reduction, with an equal or better performance and reduced manufacturing cost, are the main drivers for new packaging concepts. The embedding of active and passive components offers a wide range of benefits and potentials. With the use of laminate based technology concepts, components can be moved from surface mount into the build-up layers of substrates by embedding and by that, the third dimension will be available for further layers or assemblies. This paper will briefly discuss the necessary process steps of the embedded chip technology, which is based on printed circuit board manufacturing processes, and will also demonstrate the transfer of the technology from a smaller size lab scale equipment environment to an industrial comparable process line, capable of processing large panel formats up to 18” x 24”. The paper will also briefly describe this development and categorize today's embedding technologies. First modules with embedded chips are in production in Asia, mainly for telecom and computer applications. In Europe embedding has gained a strong interest for power modules, especially in automotive applications. Main drivers are the capability for compact and thin packaging, the high reliability and cost saving potential. In a number of European cooperation projects with partners from industry and research, embedding of power chips, like IGBTS and power MOSFET, is of high interest. In this paper current achievements of these projects will be shown, especially examples of realized devices and their characteristics. The dominating technology for power chip embedding is a face-up technology. Chips are bonded with their backside (drain contact) to a Cu substrate using highly conductive adhesive or solder. Using the face up assembly, a direct contact to the backside of the die is possible, allowing a lot of benefits for driving high currents and applying an efficient thermal management for the power devices. Then Chips are embedded by vacuum lamination of prepreg or RCC (resin coated copper) layers. Via holes to the top contacts (gate and source) are formed by laser drilling. The vias are metallized using conventional Cu plating. Finally conductor structures are etched in the top Cu layer, finalizing the circuit. Details will be given about device manufacturing, related yield issues and strategies to overcome them. Finally scenarios for the implementation of embedding technology and concepts for future applications will be discussed.

UTCP: A Novel Polyimide-Based Ultra-Thin Chip Packaging Technology

Flexible materials, today, are being used already as base substrates for electronic assembly. A lot of mounted components could be integrated in flexible polyimide (PI) substrates. Very interesting advantages of integrating components into the flex are compactness and enhanced flexibility; not only the interconnection but also the components themselves can be mechanically flexible. This paper describes a PI-based embedding technology for integrating very thin silicon chips in between two spin-on PI layers, the ultra-thin chip package (UTCP). This paper discusses the different process steps in the UTCP production and also presents the interconnection test results realized with this technology.

Linking nanotechnology to gigawatts: Creating building blocks for smart PV modules

AbstractCost reduction, expressed commonly as a unit cost/Wp on the level of solar cells, PV modules and systems, is the overarching theme of the major part of worldwide activities in the field of photovoltaics. Obviously, this is the condition sine qua non to be met for reaching economical viability of solar photovoltaic energy. We already outlined 1 earlier that a number of nanotechnologies developed for advanced Si‐based nanoscale CMOS transistors might also be very useful for the race toward crystalline Si solar cells with higher efficiency and lower cost. The focus on this cost parameter might, however, obscure the growing need to add more functionality to the PV system if photovoltaic energy is to play an important role in the electricity generation scenarios of the future 2. In the view of the authors much of this added functionality could be integrated at the module or even within the module by using a number of microscale and nanoscale technologies. This added functionality on PV‐module level might in first instance aim at an increase of energy yield by adding electronic components allowing to minimize the effect of shadowing losses by allowing a certain degree of reconfigurability of the PV module. Eventually, this might also reach out further by integrating the DC–AC inverter with the module (allowing to reduce DC losses) and in the end even other components integrating control and interaction functions with the electricity grid. In this paper we describe the philosophy behind the concept of the “Smart PV module” as well as two crucial technologies to realize this concept: the embedding technology for cells and components in the so‐called U module and the development of a low‐cost technology for reliable high‐power components based on GaN‐on‐Si, enabling the high‐frequency switching transistors in the DC–DC or DC–AC converters or the low‐loss switches in a “reconfigurable” U module. Besides the well‐spread conviction that nanotechnological aspects will lead to advances in terms of solar cell performance and lower cell costs, the message which we would like to convey is the fact that the development of miniaturized components using advances in micro‐ and nanotechnology are also very likely to affect the development of the “smart PV module” concept, providing ground for the statement “linking nanoscale to gigawatts.” Copyright © 2010 John Wiley & Sons, Ltd.

Multimodal literacy: What does it mean for classroom practice?

Changes to literacy pedagogy are gradually occurring in classrooms in response to contemporary communication and learning contexts. These changes are diverse as teachers and educational researchers attempt to design new pedagogy to respond to the potential of digital technologies within existing curriculum and assessment policies. This paper discusses evidence from recent classroom research where 16 teachers worked in teams in nine primary school classrooms to develop new ways of embedding technology for literacy learning. Data from the nine case studies provides evidence that teachers can combine the teaching of print-based literacy with digital communications technology across a range of curriculum areas. Findings from this research confirm that literacy needs to be redefined within current curriculum contexts, particularly in light of the emergence of a national curriculum. New descriptors of language and literacy criteria are proposed within the framework of multimodal literacy, the literacy that is needed in contemporary times for reading, viewing, responding to and producing multimodal and digital texts.

The Regulation of Gaze and Capture

The increasing use of the body for embedding technology as well as the convergence of multiple features in mobile telephony have made image capture an important phenomenon that presents new ways to capture events and their constructs, which cast new forms of gaze into everyday life. The ways in which one captures and gazes has increasing ethical, legal and social implications for societies. The civilian gaze through mobile recording devices can be empowering in terms of holding authorities accountable, but it can equally debilitate societies by transgressing privacy and enabling new forms of voyeurism and deviance. In recognition of this, many governments and authorities are restricting the ways in which we capture and upload images. This paper looks at how this image economy is creating new ways of looking and how the new rules are, for different reasons, seeking to curb this architecture of capture.

The effect of interface topography for Ultrasonic Consolidation of aluminium

Ultrasonic Consolidation (UC) is an additive manufacturing technology which is based on the sequential solid-state ultrasonic welding of metal foils. UC presents a rapid and adaptive alternative process, to other metal-matrix embedding technologies, for ‘smart’ metal composite material production. A challenge that exists however relates to optimising, for bond density and plastic flow, the interlaminar textures themselves that serve as the contact surfaces between the foils. UC employs a sonotrode connected to a transducer to exude ultrasonic energy into the metal foil being sequentially deposited. This sonotrode to metal contact imparts a noteworthy topology to the processed metals surface that in turn becomes the crucial substrate topology of the subsequent layers deposition. This work investigated UC processed Al 3003 samples to ascertain the effect of this imparted topology on subsequent layer deposition. Surface and interlaminar topology profiles were characterised using interferometry, electron and light microscopy. The physical effect of the topology profiles was quantified via the use of peel testing. The imparted topology profile was found to be of fundamental significance to the mechanical performance and bond density achieved within the bulk laminate during UC. The UC process parameters and sonotrode topology performed a key role in modifying this topology profile. The concept of using a specifically textured sonotrode to attain desired future smart material performance via UC is proposed by the authors.

Prekäre Balance: Ingenieurwissenschaft zwischen Innovations- und ReflexionskulturenDelicate Balance: Engineering Science between Innovation Cultures and Reflexive Cultures

Sustainable development is a great challenge for both research and education in engineering sciences. It requires not only that a specific technology meets specific functional needs, but also that the technology is developed under democratic decision processes. I therefore argue that we need to reflect on the specific structure of the epistemic culture of engineering sciences. Engineering sciences are characterized by a constellation of so-called innovation cultures and reflexive cultures. Innovation cultures are formed around an important scientific-technical principle, like electronics or the transformation of chemical substances. Reflexive cultures analyze the specific structure of technological environments in order to avoid risks related to a specific technology. I elaborate on the innate tension between innovation cultures and reflexive cultures, using synthetic chemistry and synthetic biology as main examples. I conclude that technical education has to 1. become more aware of the epistemic structure of engineering sciences, and 2. address the specific socio-political processes of embedding technology in society, thus promoting democratic decisions on innovations and their risks.

Chip-last Embedded Actives and Passives in Ultra-Miniaturized Organic Packages with Chip-First Benefits

Embedded actives and passives are being pursued by chip-first and wafer-level fan-out approaches to address high functionality and miniaturization. A next generation embedding alternative- “chip-last embedding”, which retains all the benefits of chip-first, has been demonstrated at Georgia Tech for complex multi-component heterogeneous systems. This paper presents detailed results from the first demonstration of this novel technology called Embedded MEMS, Actives and Passives (EMAP) with Chip-Last (CL) interconnections. This technology is targeted at highly integrated modules and systems with multiple 2D and 3D ICs for RF, Digital, Analog, MEMS and passive devices. Ultra-thin (55μm) silicon test dies were embedded in a 60μm deep cavity within 6-metal layer substrates yielding a total module thickness of 0.22mm. The robustness of substrate materials and processes was demonstrated using thermal cycling of the blind-vias and through-holes. The embedded IC was bonded to the substrate at 160°C by ultra-fine pitch (30–50μm) and low-profile (10–15μm) Cu-to-Cu interconnections with polymer adhesives. Two different die-sizes 3mm × 3mm and 7mm × 7mm were investigated for reliability performance of these interconnections, which passed 1000 thermal cycles, in addition to Highly Accelerated Stress Test (HAST) and High Temperature Storage Test (HTS). Comprehensive analysis of new materials and processes used in the chip-last embedding technology has been carried out demonstrating the advantages and robustness of this promising technology. Due to manufacturing process simplicity and unparalleled set of benefits, the chip-last technology provides the benefits of chip-first while enabling highly miniaturized, multi-band, high performance modules with embedded actives and passives.

Decentralized coordinated control for a group of aircraft

The task of decentralized coordinated control for vertical trajectory movement of a group of different types of pilotless aircraft is considered here. The aircraft do not exchange information. Remote control of each plane is realized by a ground-based command post with a radio channel. An approach to decentralized control with model coordination is used for a compound system with local multiple-input multiple-output (MIMO) subsystems. The approach is based on the results of system embedding technology.

Preface

Journal Article Preface Get access Caroline Bardini, Caroline Bardini Caroline Bardini is Associate Professor at the Mathematics Department of Université Montpellier 2, France. Caroline's; background is in pure mathematics (University of São Paulo, Brazil). She has specialized in Mathematics Education (Paris 7, France). Her research interests revolve around students' mathematical thinking. She has a keen interest on both examining the impact of technology in mathematics education as well as building bridges between epistemology and mathematics education. She is involved in the teaching of mathematics, epistemology and mathematics education for undergraduate and graduate students. Search for other works by this author on: Oxford Academic Google Scholar Adrian Oldknow Adrian Oldknow Adrian Oldknow is Emeritus Professor at the University of Chichester, UK. He has retired from teaching but continues to work with teachers and schools on embedding technology effectively to enhance learning and teaching in mathematics and in integrated approaches to STEM. He is past co-editor of Teaching Mathematics and its Applications. Search for other works by this author on: Oxford Academic Google Scholar Teaching Mathematics and its Applications: An International Journal of the IMA, Volume 28, Issue 4, December 2009, Page 163, https://doi.org/10.1093/teamat/hrp029 Published: 01 December 2009

Development of remote control and monitoring of web-based distributed OPC system

This paper focuses on implementing remote control and monitoring of a web-based distributed OLE for Process Control (OPC) system. Remote monitoring and control of OPC-based systems realized at N different local control points on the Internet are achieved by using a distributed OPC (DOPC) architecture. In this proposed architecture, every local control center can control and monitor every other control point. DOPC architecture is developed by using an OPC standard created for the automation industry. This OPC was developed as an industrial standard using Microsoft's Object Linking and Embedding (OLE) technology. OPC enables different control devices to communicate with each other by exchanging data. This proposed architecture permits different OPC-based process control architectures from a wide range of fields to communicate with each other. Thus, OPC-based local control systems located in different places can communicate with each other on the Internet without using bus architecture. The basic functions of the proposed system were implemented using the Delphi software package. Local control architectures developed at N points can communicate with each other and a remote control point on a dynamic web page constructed using Active Server Pages (ASP). Consequently, the proposed DOPC architecture allows the user to control and monitor local systems from any location with internet access, and to implement data exchange between N OPC points.

The Effect of the Integration of Computing Technology in a Science Curriculum on Female Students' Self-Efficacy Attitudes

Females are underrepresented in technology-related careers and educational programs; many researchers suggest this can be traced back to negative feelings of computer self-efficacy developed as early as the age of 10. This study investigated the effect of embedding technology into a 5th grade science classroom and measuring its effect on self-efficacy beliefs of young females. During a 1-semester trial, students in an experimental group used tools such as Kidspiration©, Keynote©, and Promethean© ActivBoard for specific assignments; students in a control group were not exposed to technology integrated specifically into the science curriculum. Our results indicated that the careful selection and use of computing technology led to higher levels of perceived importance and self-efficacy toward technology by female students.

3D Process Integration – Requirements and Challenges

AbstractHeterogeneous system integration is one of the key topics for future system integration. Scaling of System on Chip (SoC) alone does not address today's requirements of smart electronic systems in terms of performance, functionality, miniaturization, low production cost and time to market. The traditional microelectronic packaging will more and more convert into complex sys-tem integration. ‘More than Moore’ will be required due to tighter integration of system level components at the package level. This trend leads to advanced System in Package solutions (SiP) which require the synergy and a combination of wafer level and board integration technologies and which are rapidly evolving from a specialty technology used in a narrow set of applications to a high volume technology with wide ranging impact on electronics markets especially due to the high volume and very cost competitive consumer and communication market. Advanced SiP approaches explore the third dimension which results in complex system architectures that also require, beside new technologies and improved materials, adequate system design tools and reli-ability models. One of the most promising technology approaches is 3D packaging which in-volves a set of different integration approaches including stacked packages, silicon interposer with Through Silicon Vias (TSV) and embedding technologies. The paper highlights future sys-tem and potential technical solutions.

How to make chip integration technology suitable for high volume production

PurposeThis paper aims to present an overview of existing component embedding methods and to show the differences of the new embedding method called SEAG iBoard.Design/methodology/approachIn most existing embedding technologies bare dies are embedded and contacted to the PCB by through hole plating technologies of the PCB industry. The new method uses a preassembled interposer for embedding which leads to rewiring of the chip contacts to larger pads on the interposer. In a next step passive components will be added to the active die on the same interposer.FindingsThe use of an interposer for embedding leads to a better compatibility of chip processes and PCB processing. Unlike other approaches, the PCB processes can be kept more or less the same as for standard production. Therefore, this new method is suitable for volume applications. The method also shows competitive advantages. Up to now the reliability tests showed a very high reliability of interconnects between the Si‐chip and PCB. Up to 5,000 TCT between −40° and 140°C could be demonstrated. These tests have been performed with daisy chain test chips.Research limitations/implicationsThe qualification results have to be confirmed with functional chips. The principle of this technology is to receive larger interconnection pads by the use of an interposer. Therefore, this technology might have limitations, where lengths of signal paths play the dominant role.Originality/valueThe paper shows how problems in the existing embedding technologies can be overcome. It shows that the preconditions for high reliability at reasonable cost are given.

The cultural impact of an in-depth consultation on the University of Nottingham A bottom-up approach

AbstractThis project aimed to ascertain from those involved in the research process the kinds of electronic tools that would most support them in their work. This information was used to inform and steer development of new tools and resources delivered via secure technology. The approach was predominantly bottom-up with a huge emphasis placed on effective consultation with practitioners. Honest two-way communication between developers and practitioners was an essential part of the process of embedding new ideas and technologies. In seeking to deliver the requirements suggested, the team identified a much wider need for collaboration across many other University departments.