Embedded Wafer Level Package Research Articles

Development of Package-on-Package Using Embedded Wafer-Level Package Approach

The ever-increasing demands of higher performance, multiple functions, higher density, and lower cost mandate the reduction of the I/O pitch on the die as well as on the package. Pitch specifications of current substrate technologies do not match the stringent fine-pitch I/O requirements. Combining embedded wafer-level package (EMWLP) and package-on-package (PoP) technologies yields a preferred solution providing fan-out area to route the fine-pitch I/Os of the chip to large-pitch I/Os on to the extra area of fan-out EMWLP packages and allows the use of conventional substrate technology. However, there are many challenges to realizing the PoP of EMWLP packages. They include the die shift during the reconstruction process, double-sided reroute distribution line (RDL), and through-mold via (TMV) connections on a thin bottom package. The assembly of EMWLP and PoP, thermal management of PoP packages, and their reliability are also major concerns. This paper describes the development of an EMWLP PoP of 12 mm × 12 mm footprint with 432 I/Os and the adoption of TMV to enable PoP connections. The top package circuitry is accessed through TMVs in the bottom package with double-sided RDL. Solid TMV and side-wall-plated TMV are demonstrated in the EMWLP. Mechanical modeling of the PoP is conducted to optimize the structures of the packages for good reliability performance of the PoP. Thermal dissipation of the PoP is another area of concern, because the thermal path of the top package is limited in mobile applications. The thermal performance of the developed PoP was analyzed by thermal modeling and was successfully validated by thermal characterization of the PoP module. The developed PoP successfully passed the JEDEC standard reliability tests such as moisture sensitivity level 3 test; the unbiased highly accelerated stress test for 96 h, 500 air-to-air thermal cycling ( -40°C to 125°C), and 30 drop tests.

Mechanical Analyses of Advanced Multi-Chip Embedded Wafer Level Packages

ncreasing functionality accompanied with device miniaturization in microelectronics has led to increased market demand for packages with small form factor. Over the years, embedded wafer level packaging (EWLP) has become an attractive option since it allows a reduction in package size and height. In the EWLP approach, the singulated dies are embedded within the molding compound through the wafer level compression molding process. For this study, critical mechanical challenges such as die shift and thermal cycling performance of a multi-chip embedded wafer level package (MCEWLP) are addressed through numerical modeling. For improved accuracy in die shift predictions, both mechanical effects and fluidic effects need to be taken into account. Mechanical effects account for around 75% of the die shift while fluidic effect contributes to the remaining 25%. It is shown that reducing the die size and the inclusion of UBM as a buffer layer can effectively increase the fatigue life of the packages.

Effect of permanganate treatment on through mold vias for an embedded wafer level package

In this study, a through mold via (TMV) interconnect was developed for an embedded wafer level package (EMWLP) to enable 3D packing applications. The effects of the shape and surface roughness of the epoxy molding wafer on the quality of electroless Cu metallization were investigated for the vertical interconnection. The mold compound is a composite material composed of epoxy resin and filler particles. Therefore, the effect of the amount of filler particles was studied to optimize the shape of the epoxy molding by applying two types of laser drilling modes. In addition, the electroless Cu plating process was optimized to deposit a Cu seed layer along the TMV sidewall. To optimize the TMV process, a desmear process was applied to improve the shape of the TMV sidewall and adhesion between the epoxy molding compound and the dielectric polymer for multilayer metallization.