Specification Of Embedded Systems Research Articles

On the verification of system-level information flow properties for virtualized execution platforms

The security of embedded systems can be dramatically improved through the use of formally verified isolation mechanisms such as separation kernels, hypervisors, or microkernels. For trustworthiness, particularly for system-level behavior, the verifications need precise models of the underlying hardware. Such models are hard to attain, highly complex, and proofs of their security properties may not easily apply to similar but different platforms. This may render verification economically infeasible. To address these issues, we propose a compositional top-down approach to embedded system specification and verification, where the system-on-chip is modeled as a network of distributed automata communicating via paired synchronous message passing. Using abstract specifications for each component allows to delay the development of detailed models for cores, devices, etc., while still being able to verify high-level security properties like integrity and confidentiality, and soundly refine the result for different instantiations of the abstract components at a later stage. As a case study, we apply this methodology to the verification of information flow security for an industry-scale security-oriented hypervisor on the ARMv8-A platform and report on the complete verification of guest mode security properties in the HOL4 theorem prover.

COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Hardware-software co-synthesis starts with an embedded-system specification and results in an architecture consisting of hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. In this paper, we present a co-synthesis algorithm COSYN, which starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded-system architecture meeting these constraints. It supports both concurrent and sequential modes of communication and computation. It employs a combination of preemptive and nonpreemptive static scheduling. It allows task graphs in which different tasks have different deadlines. It introduces the concept of an association array to tackle the problem of multirate systems. It uses a new task-clustering technique, which takes the changing nature of the critical path in the task graph into account. It supports pipelining of task graphs and a mix of various technologies to meet embedded-system constraints and minimize power dissipation. In general, embedded-system tasks are reused across multiple functions. COSYN uses the concept of architectural hints and reuse to exploit this fact. Finally, if desired, it also optimizes the architecture for power consumption. COSYN produces optimal results for the examples from the literature while providing several orders of magnitude advantage in central processing unit time over an existing optimal algorithm. The efficacy of COSYN and its low-power extension COSYN-LP is also established through their application to very large task graphs (with over 1000 tasks).

High-Level Embedded System Specifications Based on Process Activation Conditions

High-level specifications for the behaviour of information processing systems consist of data and control flow descriptions as well as of timing requirements, which are to be met by feasible implementations. In contrast to systems specified as task graphs this approach is based on a functional partitioning. A process net description with conditional process activation is proposed. Furthermore, the simulation of token flow leads to a schedule that supports investigations of the timing analysis for the proposed Codesign Model (CDM). Predictions of the delay between any two processes of the system are also possible, as well as the processing speed of primary inputs and outputs, iteration times of determined periods, and hence, all derivable time criteria. A formal notation of process nets as cyclic graphs is given, which is shown to be useful for the description of complex digital embedded systems. The properties of the processes involved are detailed. In general, scheduling with resource allocation on a graph structure, as discussed in this paper, is NP-complete. However, the advocated simulation method delivers detailed information on conditional paths of data and control flow in a CDM. The simulation can be interrupted at any point in time for an evaluation of corresponding results and for a subsequent refinement of the CDM. The outlined approach is intended for a capture and an accessment of specifications in the conceptual phase of system development. Resulting advantages and some restrictions are demonstrated by means of an image processing system.

Specification and Design of Embedded Systems

Specification and Design of Embedded Systems

MOGAC: a multiobjective genetic algorithm for hardware-software cosynthesis of distributed embedded systems

In this paper, we present a hardware-software cosynthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes real-time heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard real-time constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and point-to-point communication links allows a number of link types to be used in an architecture. Application-specific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multirate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single cosynthesis run to produce multiple designs that trade off different architectural features. Experimental results indicate that MOGAC has advantages over previous work in terms of solution quality and running time.

Specification and design of embedded hardware-software systems

Embedded-system specification and design consists of describing a system's desired functionality and mapping that functionality for implementation by a set of system components such as processors, ASICs, memories, and buses. This paper discusses the key problems of system specification and design, including specification capture, design exploration, hierarchical modeling, software and hardware synthesis, and cosimulation. The authors highlight existing tools and methods for solving those problems and describe a specify-explore-refine methodology for meeting today's embedded-system product development requirements. >

Embedded system specifications and transformation into Occam

One of the most important stages in the development of any real-time system is the generation of a consistent design that satisfies an authoritative specification of requirements. Management of the development of complex real-time systems requires the appropriate level of decomposition, encapsulation and abstraction, and their implementation requires languages incorporating concurrency and error-handling facilities. This paper shows that Modular Object Oriented Notation (MOON) specifications cater for the specification of real-time systems, which can be suitably transformed for concurrent implementation using Occam and similar languages.