Embedded Systems Market Research Articles

Measuring the Efficiency of Cache Memory on Java Processors for Embedded Systems

Java, with its advantages as being an overspread multiplatform object oriented language, has been gaining popularity in the embedded system market over the years. However, because of its extralayer of interpretation, it is also believed that it is a slow language while being executed. Nevertheless, when this execution is done directly in hardware, Java advantages caused by its stacknature start to appear. One of these advantages concerns memory utilization, impacting in less accesses and cache misses. In this work we analyze this impact in performance and energy consumption,comparing a Java processor with a RISC one based on a MIPS architecture with similar characteristics.

Short informative title: Towards a new tendency in embedded systems in mechatronics for the engineering curricula

AbstractThis paper presents a robot motion controller for an undergraduate laboratory study program. It is designed to help the students learn and to assess specific learning outcomes proposed by ABET by solving a real‐life problem. The main objective of this project is to enable the engineering students to learn some core concepts about embedded systems and motion controllers for robotics by applying them in practice. Also, the proposal shows how to introduce the students to a new tendency in the embedded system market, namely, an All Programmable System on a Chip (SoC). This methodology incorporates interdisciplinary knowledge, technical and professional skills required for pursuing a successful career. In the present study, we surveyed the observations and interests of students towards the learning process, and the results indicate that the inclusion of the robot prototype has a significant impact on providing students with new learning outcomes.

INTEGRATED DOMAIN-SPECIFIC PROGRAMMING ENVIRONMENT FOR HETEROGENEOUS MANYCORE PLATFORMS

Different classes of problems on the embedded systems market and its needs make manufacturers of embedded systems to design heterogeneous many/multi core hardware platforms. Such platforms includes dozens of different cores: CPU, GPU, DSP, FPGA etc. That makes them incredibly hard to program, especially in case when domain experts are involved in the development process. Usually, domain expert has knowledge in his domain area, but does not fully understand the specificity of programming for heterogeneous manycore platforms. In this article, we propose the complex technology and tools that allows involving domain experts in software development for embedded systems. The proposed technology has various aspects and abilities that can be used to build verifiable and portable software for a wide range of heterogeneous embedded platforms.

AnyNoC: new network on a chip switching using the shared-memory and output-queue techniques for complex Internet of things systems

Recently, the Internet of things (IoT) has attracted a lot of attention owing to its versatile applications by enabling numerous things/objects to collect and exchange data via Internet. Despite the promising role of IoT, there exists the problem of integrating many heterogeneous functions into an embedded and complex IoT system. Meanwhile, in the past decade, we have also envisioned a paradigm shift in the embedded system market toward the system on a chip (SoC) by integrating all components into a single chip. But the on-chip communications of IoT systems remain an important and challenging issue. This work proposes a new network on a chip (NoC) switching, AnyNoC, employing the shared-memory and output-queue techniques implemented using the efficient dynamic link list, particularly suitable for the IoT SoC. The proposed high-level design can achieve the optimal performance by sharing the data buffer among all ports and eliminating the head-of-line blocking problem, resulting in a virtual point-to-point characteristic without the interruption of slow devices or congestion conditions in other ports. Moreover, the proposed architecture can minimize the required memory size by virtually sharing all buffers among all ports, resulting in one queue needed for each outbound port and totally N queues are required, where N denotes the number of ports. Therefore, compared to the famous wormhole switching, the proposed NoC architecture features lower cost and higher performance, which can approach the theoretical upper bound. Moreover, for a \(16\times 16\) network, the performance gain of the throughput of the proposed switching compared to the popular wormhole switching is about \(40\%\).

An Intelligent Vehicular Traffic Signal Control System with State Flow Chart Design and FPGA Prototyping

The problem of vehicular traffic congestion is a persistent constraint in the socio-economic development of Pakistan. This paper presents design and implementation of an intelligent traffic controller based on FPGA (Field Programmable Gate Array) to provide an efficient traffic management by optimizing functioning of traffic lights which will result in minimizing traffic congestion at intersections. The existent Traffic Signal system in Pakistan is fixed-time based and offers only Open Loop method for Traffic Control. The Intelligent Traffic Controller presented here uses feedback sensors to read the Traffic density present at a four way intersection to provide an efficient alternative for better supervisory Control of Traffic flow. The traffic density based control logic has been developed in a State Flow Chart for improved visualization of State Machine based operation, and implemented as a Subsystem in Simulink and transferred into VHDL (Hardware Description Language) code using HDL Coder for reducing development time and time to market, which are essential to capitalize Embedded Systems Market. The VHDL code is synthesized with Altera QUARTUS, simulated timing waveform is obtained to verify correctness of the algorithm for different Traffic Scenarios. For implementation purpose estimations were obtained for Cyclone-III and Stratix-III.

ParMiBench - An Open-Source Benchmark for Embedded Multiprocessor Systems

Multicore processors are the main computing platform in laptops, desktop, and servers today, and are making their way into the embedded systems market also. Using benchmarks is a common approach to evaluate the performance of a system. However, benchmarks for embedded systems have so far been either targeted for a uni-processor environment, e.g., MiBench,or have been commercial, e.g., MultiBench by EEMBC. In this paper, we propose and implement an open source benchmark,ParMiBench, targeted for multiprocessor-based embedded systems. ParMiBench consists of parallel implementations of seven compute intensive algorithms from the uni-processor benchmark suite MiBench. The applications are selected from four domains:Automation and Industry Control, Network, Office, and Security.

DFTL

Recent technological advances in the development of flash-memory based devices have consolidated their leadership position as the preferred storage media in the embedded systems market and opened new vistas for deployment in enterprise-scale storage systems. Unlike hard disks, flash devices are free from any mechanical moving parts, have no seek or rotational delays and consume lower power. However, the internal idiosyncrasies of flash technology make its performance highly dependent on workload characteristics. The poor performance of random writes has been a cause of major concern, which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the Flash Translation Layer (FTL), which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-based Flash Translation Layer (DFTL), which selectively caches page-level address mappings. We develop a flash simulation framework called FlashSim. Our experimental evaluation with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: (i) improved performance, (ii) reduced garbage collection overhead and (iii) better overload behavior compared to state-of-the-art FTL schemes. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared to a state-of-the-art FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%.

Rico: a security proxy for mobile code

Security technology suitable for the burgeoning embedded system market has not been widespread. Untrusted code downloaded from the Internet poses numerous security risks due to the possible presence of viruses or other malicious entities. System administrators typically administer one or more administrative domains making policy management for mobile code a challenge because of the diverse security rules that must be adhered to. In this paper, we introduce Rico, a binary rewriting, security policy and code management system that sits between clients and servers. The system interposes itself between a client that downloads mobile code and the target server to provide the system administrator a means to secure untrusted code by rewriting it. The system supports the following features: (1) A security policy editor that simplifies policy writing with frame wizards, syntax reminders and error checking. (2) Third-party policy incorporation enabling reuse of security policies created by trusted third parties. (3) Policy composition, the capability of combining multiple security policies into one logical policy that can be applied to a mobile program. (4) Efficient security management supported by a graphical user interface and a self-training database.

On the buses [high-speed serial bus

The physical limitations of parallel bus technology are now the principal constraint on computer performance. However, towards the end of 2004, the first of the new generation of PCs incorporating the latest high-performance serial buses will come into use. The new buses will enable PCs to be more compact, powerful and cost-effective. What is more, the ramifications of these changes are extending beyond the confines of the PC into the embedded system market where some of the latest telecoms systems are already using the new serial buses to great effect.

A Conversation with Jim Ready

Linux may well play a significant role in the future of the embedded systems market, where the majority of software is still custom built in-house and no large player has preeminence. The constraints placed on embedded systems are very different from those on the desktop. We caught up with Jim Ready of MontaVista Software to talk about what he sees in the future of Linux as the next embedded operating system (OS).

Embedding windows

Not content with dominating the desktop, Microsoft is now testing the Windows standard against the taxing requirements of the embedded systems market. The author outlines the implications for developers.