Embedded Silicon Germanium Research Articles

Impact of CnRx Structure on Soft Error Rates of Flip-Flop Designs at 22-nm FD SOI Node

Embedded Silicon Germanium (eSiGe) is used in the channel region of PFET devices at the 22-nm FD SOI node. The use of eSiGe results in channel regions becoming strained, which results in better hole mobility and increased performance. However, if the active diffusion regions are too short on each side of a PFET gate, then the effect of channel strain is reduced, and performance is reduced. The Continuous Active Diffusion (CnRx) layout construct suggested by the foundry is a way to help keep channel strain present within a single cell design. In this paper the CnRx construct is implemented in a 22-nm FD SOI test chip and soft error rates of stacked-transistor flip-flops are shown to increase with heavy ion irradiation. The effect of channel strain on PFETs results in higher collected charges from ion strikes, and charges are more easily passed between adjacent transistors through strained channels. However, with careful schematic and layout design, these effects can be mitigated to produce both high performance and radiation tolerant cells using the CnRx construct.

Observation of semiconductor device channel strain using in-line high resolution X-ray diffraction

In-line high resolution X-ray diffraction has been used to analyze embedded silicon-germanium (eSiGe) epitaxially grown in the source/drain regions of complementary metal-oxide-semiconductor devices. Compared to blanket films, the diffraction from patterned devices exhibited distinct features corresponding to the eSiGe in the source/drain regions and Si under the gate and SiGe. The diffraction features modulated with structural changes, alloy composition, and subsequent thermal processing. Reciprocal space measurements taken around the (224) diffraction peak revealed both in-plane (h) and out-of-plane (l) lattice deformation, along with features corresponding to the regular spacing between the gates.

Context Dependence Effects in Si/SiON Based Advanced CMOS Devices

Significant sources of mechanical stress have been deliberately added into the active silicon of CMOS devices to improve carrier mobility. These include Dual Stress nitride Liners (DSL) and embedded Silicon Germanium (eSiGe) in the source and drain regions of PMOS transistors. Moreover, as transistor dimensions have shrunk, unintentional sources of variation such as Shallow Trench Isolation (STI) mechanical stress and dopant redistribution due to proximity to STI boundary or the well implant boundary (WPE) have also increased the systematic transistor variability. This increased systematic variability has impacted the product yield and provided the impetus to include context dependence in SPICE models of transistor electrical performance. This paper outlines a rigorous approach to not only quantify the physical mechanisms and impact of context effects, but also how to model these effects on the electrical transistor performance and various strategies to mitigate the impact of these context dependencies on digital circuit performance.

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

We investigate the effect of implantation and annealing on 45 nm node transistors with embedded silicon–germanium source and drain, using UV Raman spectroscopy. Direct measurements of the channel strain indicate that the strain relaxed after implantation is recovered partially after annealing. Recovery of channel strain depends on annealing conditions. Our results show that a low-temperature, long-duration anneal results in a greater channel strain compared to a high-temperature, short-duration anneal. When a high-temperature anneal is needed for fabricating transistors, a two-step anneal involving a low-temperature furnace anneal prior to a high-temperature rapid thermal anneal can be beneficial for recovering channel strain.

Impact of Implantation and Annealing on Channel Strain of Transistors with Embedded Silicon–Germanium Source and Drain

We investigate the effect of implantation and annealing on 45 nm node transistors with embedded silicon–germanium source and drain, using UV Raman spectroscopy. Direct measurements of the channel strain indicate that the strain relaxed after implantation is recovered partially after annealing. Recovery of channel strain depends on annealing conditions. Our results show that a low-temperature, long-duration anneal results in a greater channel strain compared to a high-temperature, short-duration anneal. When a high-temperature anneal is needed for fabricating transistors, a two-step anneal involving a low-temperature furnace anneal prior to a high-temperature rapid thermal anneal can be beneficial for recovering channel strain.

ESiGe Global and Micro Loading Effect Study in High Performance 45nm CMOS Technology

The embedded silicon germanium (eSiGe) is widely applied in advanced CMOS device fabrication to boost PMOS channel mobility. Beside selectivity, defect control and thermal compatibility, one big challenge of epitaxy growth SiGe process is loading effect between different product and different features. In this work, two precursors of SiH4 and SiH2Cl2 (DCS) were applied for SiGe epitaxy growth respectively. Their impact on embedded silicon germanium global and micro loading was investigated also. The results reveal some solutions to minimize the loading effect such as proper precursor selection, partial pressure optimization and silicon open space constraint.

An x86-64 Core in 32 nm SOI CMOS

This paper describes the 32 nm implementation of an AMD x86-64 core. It occupies 9.69 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3 GHz. This AMD chip is fabricated in Global Foundries' 32 nm SOI and uses high-K metal gate technology. The process uses dual strain liners and eSiGe (embedded Silicon Germanium) to improve performance. Transistors are fabricated in various threshold voltages and lengths to facilitate performance/leakage tradeoffs. The core incorporates numerous design and power improvements to enable an operating range of 2.5 W to 25 W and a near zero-power gated state, which makes the core well-suited to a broad range of mobile and desktop products including multicore SOC designs.

Fully Depleted Strained Silicon-on-Insulator p-MOSFETs With Recessed and Embedded Silicon–Germanium Source/Drain

Strained p-MOSFETs with recessed and embedded silicon-germanium (eSiGe) source/drain (S/D) are fabricated on either silicon-on-insulator (SOI) or strained SOI (sSOI) substrates of 15-nm body thickness. For a gate voltage overdrive of -1 V and a gate length L of 60 nm, p-MOSFETs on SOI (sSOI) with eSiGe exhibit a 37% (18%) saturation drive current enhancement compared to standard sSOI structures with Si S/D. The low field mobility and series resistance are extracted in order to understand the performance boost induced by the eSiGe process. The significant I_ON improvement of SOI pMOS with eSiGe S/D compared to sSOI pMOS with Si S/D is attributed to a 65% mobility enhancement and to a 30% series-resistance reduction with respect to sSOI pMOS with Si S/D at L = 60nnm.

An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow

This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon–germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.

Challenges to quantitative energy-dispersive X-ray spectrometry and its application to graded embedded silicon–germanium for high-performance complementary metal oxide semiconductor devices

Energy-dispersive X-ray spectrometry (EDXS) in the transmission electron microscope (TEM) is applied for accurate spatially resolved quantitative chemical analysis of SiGe structures implemented into high-performance complementary metal oxide semiconductor (CMOS) transistors. For fast and high-quality TEM target specimen preparation, an advanced focused ion beam (FIB)-based lift-out technique employing Be half ring grids is developed to significantly minimize post-specimen scatter artifacts during EDXS data recording. Based on systematic variation of acquisition parameters (dwell time, sampling area) at fixed beam current, the influence of electron irradiation on microstructure and composition of SiGe alloys is studied, and a critical electron fluence for beam-induced damage is identified. While chemical analysis is unaffected for smaller values, higher electron fluences cause atom displacement by surface sputtering. Applying optimal acquisition parameters for accurate composition analysis at standard TEM settings, spatially confined graded embedded SiGe cavities, introduced into the CMOS process flow to transfer compressive stress into the pMOS transistor channel, are characterized.

Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications

In this paper, we describe our triple sidewall spacer scheme to achieve 45 nm ground rule for high-performance applications. This triple sidewall spacer scheme uses three kinds of sidewall spacers, in which the first sidewall is used for the source/drain extension implantation offset (SW1), the second is for the p-channel field effect transistor (PFET) embedded silicon germanium offset (SW2), and the third spacer is for the deep source/drain implantation offset (SW3). We also evaluated the impact of sidewall spacer materials and structures on device characteristics. After optimizing each sidewall spacer material and structure including offset width, we successfully demonstrated identical device characteristics with the minimum poly-pitch layout while minimizing layout dependence. This sidewall spacer scheme has the capability to achieve the 45 nm ground rule, and our sidewall spacer design is mature and suitable for 45-nm-node high-performance applications.

Strain relaxation in transistor channels with embedded epitaxial silicon germanium source/drain

We report on the channel strain relaxation in transistors with embedded silicon germanium layer selectively grown in source and drain areas on recessed Si(001). Nanobeam electron diffraction is used to characterize the local strain in the device channel. Our results show that strain is reduced in the device channel regions after implantation and thermal anneal.

Novel enhanced stressors with graded encapsulated SiGe embedded in the source and drain areas

An advanced CMOS scheme for the integration of a graded epitaxial Silicon Germanium (SiGe) layer is presented. SiGe is deposited into the source drain regions right after gate formation to create compressive strain in the transistor channel of the pMOSFETs and thus improve charge carrier mobility. The SiGe layer is exposed to subsequent process steps such as cleaning, implantation and annealing which cause erosion and dopant loss. This effect becomes more severe with increasing Ge content, which is wanted to increase stress in the channel. The negative effect of SiGe erosion on DC transistor performance is shown in this paper and how it can be reduced by optimized SiGe deposition utilizing a two layer stack with different Ge content. First a film with higher Ge concentration is deposited followed by a lower percent Ge film which is aimed to protect the SiGe film underneath. Electrical data for PMOS devices with 55 nm embedded SiGe with 20–30% Ge are presented and compared to the corresponding graded SiGe stack (25–30%, 50 nm with 5 nm thick 15% cap). Comparing Embedded Silicon Germanium (eSiGe) devices with 30 at% Ge, we see a 5% I DSAT improvement for the graded layer over the monolithic one.

Implant damage and strain relaxation of embedded epitaxial silicon germanium layer on silicon

The authors report on the implant damage and strain relaxation in embedded silicon germanium (SiGe) layer, selectively grown on recessed silicon (Si) (001) with different recess length (defined as [110] direction, along the conventional Si transistor channel) and the same width (defined as [1−10] direction). Similar to the implant damage in blanket epi-SiGe layers on Si (001) reported previously, they observed two defect bands, one close to the surface and the other at SiGe∕Si interface. Unlike the biaxial strain relaxation with misfit dislocations equally distributed along both the [110] and [1−10] directions in blanket epi-SiGe layers on Si (001), there is a gradual change from biaxial to uniaxial relaxation with misfit dislocations along only at the [1−10] direction and a decreasing density of misfit dislocation, with decreasing recess length.