Embedded Network Applications Research Articles

Visualizing the runtime behavior of embedded network systems: A toolkit for TinyOS

TinyOS is an effective platform for developing lightweight embedded network applications. But the platform’s lean programming model and power-efficient operation come at a price: TinyOS applications are notoriously difficult to construct, debug, and maintain. The development difficulties stem largely from a programming model founded on events and deferred execution. In short, the model introduces non-determinism in the execution ordering of primitive actions — an issue exacerbated by the fact that embedded network systems are inherently distributed and reactive. The resulting set of possible execution sequences for a given system is typically large and can swamp developers’ unaided ability to reason about program behavior. In this paper, we present a visualization toolkit for TinyOS 2.0 to aid in program comprehension. The goal is to assist developers in reasoning about the computation forest underlying a system under test and the particular branches chosen during each run. The toolkit supports comprehension activities involving both local and distributed runtime behavior. The constituent components include (i) a full-featured static analysis and instrumentation library, (ii) a selection-based probe insertion system, (iii) a lightweight event recording service, (iv) a trace extraction and reconstruction tool, and (v) three visualization front-ends. We demonstrate the utility of the toolkit using both standard and custom system examples and present an analysis of the toolkit’s resource usage and performance characteristics.

Architecture and instruction set design of an ATM network processor

Microprocessor architectures are diversifying to support niche market requirements, with growing emphasis for performance delivery on the architectural design rather than the silicon implementation. This paper outlines the architectural design, programmer's model and instruction set of a microprocessor, which adopts a novel approach to network data. In particular, Asynchronous Transfer Mode (ATM) cells are delivered to a special FIFO cache memory, located at the heart of the processor. Cell input and output is conducted at wire speed using dedicated streaming input and output hardware. Special read and write instructions then allow the cell payloads to be accessed directly, and transferred from/to the register file. Multimedia applications have previously been identified as an important market for such a network centric architecture. Therefore the paper ends with a demonstration of the power of some key instructions. A motion estimation kernel from the MPEG standard is used to exercise the architecture and instruction set. Execution speed is shown to be comparable to today's processors, using only a 400 MHz clock for a full search. The minimally resourced design is therefore suited to embedded network applications from both economic and performance standpoints.

Memory management for embedded network applications

In embedded network applications, typically a very large part of the area cost is due to memory units. Also the power for such applications is heavily dominated by the storage and transfers. Given its importance, we have developed a systematic memory management methodology in which the storage related issues are optimized as a first step. In this paper, we present our methodology for embedded network applications. It includes both a dynamic memory management stage, where the data types and virtual memory managers are defined, and a physical memory management stage, where the custom memory architecture is defined. As demonstrated on an industrial example, the application of the methodology results in a heavily power and/or area optimized custom memory architecture for a given application.